應用於低電壓操作之七電晶體靜態隨機存取記憶體電路設計

A 7T SRAM Circuit Design for Low Voltage Applications

陳來福(Lai-Fu Chen)

指導教授 ： 張孟凡

國立清華大學/電機資訊學院/電子工程研究所/碩士(2011年)

摘要

在現今的高階系統單晶片中都嵌入許多的靜態隨機存取記憶體，無非是因為它具有速度快及製程相容性高的優點。然而，在講求低功耗的系統如手持式消費產品，靜態隨機存取記憶體往往是降低功率消耗的瓶頸。於是，若能夠使其操作在低電壓下，其功率消耗便能有效的降低。但由於傳統的六電晶體記憶體細胞元受限於本身的架構，在操作電壓降低及製程微縮下，使得各樣的變異性問題一一浮現，發生存取錯誤的機率大幅提升。例如，嚴重的漏電流使得細胞元內的資料在低電壓下不易維持，所以需要一定的資料維持電壓；存取時，被選取的細胞元中的資料受到讀取干擾，而未被選取細胞元中的資料將一同會被干擾，這是因為在同一行的傳統六電晶體細胞元分享同一字線的緣故。因此，如何利用特殊的細胞元結構及周邊電路來提升在低電壓時的穩定度是相當有難度的，所以這些都是很熱門的研究課題。從先前的文獻得知，許多八到十個電晶體的新型細胞元相繼被提出，但是這些方法都必須大幅的犧牲記憶體密度，因為它們皆具有較大的細胞元面積。實際上，大多數都無法被業界採用，因為記憶體密度及成本都是業界最重視的。
有鑒於此，我們企圖提出一個具有量產機會的七電晶體細胞元。我們在傳統六晶體細胞元中加入一電晶體的退耦讀取埠，這使得它在讀取時不會干擾到細胞元內的資料，而且讀取靜態雜訊邊際與保持靜態雜訊邊際一樣。因此，在設計七電晶體細胞元時不會受限讀取穩定度及寫入能力之間不可兼得的問題，我們可以有較大的細胞元設計空間來改善寫入能力。透過墊高讀取位元線電壓之輔助電路來提升單端感測放大電路的感測邊際，並減少箝制電流對讀取電流的影響；對於未被選取之讀取字線施加電壓可抑止讀取位元線的漏電流。在寫入時，對於未被選取之細胞元，利用先讀取其資料然後將其重新寫回，如此可避免因為分享寫入字線所造成的寫入半選取干擾。另外，七電晶體細胞元只有六電晶體細胞元的面積一點一倍大。
最後我們透過六十五奈米互補式金氧半製程技術製造出一個具有三十二千字元(32-kb)容量的七個電晶體之靜態隨機存取記憶體積體電路。量測結果顯示，此積體電路的操作電壓範圍在零點三四伏至一伏之間。其中，若未使用墊高讀取位元線電壓技術時，最低操作電壓為三百七十毫伏，最高操作頻率為二十三百萬赫茲(23-MHz)；若使用墊高位元線電壓技術時，最低操作電壓為三百四十毫伏，最高操作頻率為二十二百萬赫茲(22-MHz)。

關鍵字

靜態隨機存取記憶體 ； 低電壓 ； 七電晶體

並列摘要

More and more SRAMs are used in high-end SoC, because they have many advantages such as high speed and process compatibility. However, SRAMs will be a bottleneck for decreasing power consumption in low power system such as mobile consumer electronics. Hence, if SRAMs can operate at lower voltage, its power consumption will be decreased. However, a conventional 6T SRAM cell suffer from various variations due to voltage and technology scaling, the probability of access failure will be much increased. The data of SRAM cell suffer from leakage currents at low voltage and needs a high data retention voltage. For access operation, the data of selected cell and unselected cells suffers from read and half-selected disturbance, respectively, due to they share same word line in a row. Hence, novel cell structure and peripheral circuits are used to improve the stability at low voltage especially. Some published works such as 8T~10T SRAM cells are proposed, but these decrease memory density due to larger cell area. Actually, it always cannot be accepted by industries because of cost considering.
Hence, we propose a novel 7T SRAM cell. We add 1T decoupled-read port in 6T cell, this eliminates read-disturb and makes the read SNM of 7T cell is similar to hold SNM. Hence, we have more sizing space to achieve larger write margin. Boosted read bit line (RBL) scheme is used to increase sensing margin for sense amplifier, and it decreases clamping current also. For unselected rows, VDD-driven read word line scheme is used to suppress the leakage of RBL. For write operation, read-first and write-back scheme is used for unselected cells to prevent write half-selected-disturb issue. The cell size of 7T cell is just 1.1 times that of conventional 6T cell.
Finally, 32kb 7T SRAM test chips are fabricated in 65nm CMOS technology. In measurement results, this work can operate at 0.34-V~1-V, and the VDDmin of this work is 370-mV at 23-MHz. If the boosted RBL scheme is used, the VDDmin can lower to 340-mV at 22-MHz.

並列關鍵字

SRAM ； Low Voltage ； 7T

參考文獻

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