實現在40奈米製程技術下可操縱在低操縱電壓的512Kb 8T靜態隨機存取記憶體

隨著攜帶式電子產品，像是PDA，筆記型電腦，行動手機越來越廣泛的運用，減少整個SoC晶片的能量消耗變成了一個很重要的課題。在先進的SoC晶片設計中，静態隨機存取記憶體通常佔有最大的面積，所以主宰了效能跟總能量消耗。降低操縱電壓是一個最有效可以減少總能量消耗的辦法。傳統的6顆電晶體静態隨機存取記憶因為有讀取干擾跟寫入半選擇干擾，所以並不適合操縱在低電壓。製程跟溫度的變異亦讓傳統的6T静態隨機存取記憶的穩定性嚴重下降。這篇論文提出了一個可操縱在低電壓的512Kb的静態隨機存取記憶陣列。此陣列是使用一個具有無讀取干擾跟資料感測寫入幫助的8T静態隨機存取記憶。交叉結構可以消除寫入半干擾並且可以使用位元交錯結構。可調式讀取/寫入時間追蹤複製電路，漣波位元線讀取架構跟區域位元線保持電路提高了讀取跟寫入的穩定性跟能力。借由使用具有資料感測寫入幫助的8T静態隨機存取記憶及寫入/讀取幫助電路，此記憶體陣列可以操縱在低電壓。一個512Kb的測試晶片建立在UMC的40nm製程上。經由電路佈局後的模擬顯示，在1.1伏特可操縱在502.5百萬赫茲以及在0.6伏特可操縱在28.42百萬赫茲。在1.1伏特下的寫入/讀取耗能分別為13.5微瓦/百萬赫茲及6.87微瓦/百萬赫茲。最低操縱電壓可達到0.45伏特。

關鍵字

低操縱電壓之靜態隨機存取記憶體；資料依存寫入幫助機制；漣波位元線讀取機制；區域位元線保持電路；可調式讀取/寫入時間追蹤複製電路

並列摘要

According to more and more wide-ranging usage of portable electronic devices such as PDA, notebook, cell-phone and so on, reducing the power consumption of whole SoC chip is one of the most important topics. In advanced SoC chip design, SRAM usually occupies the biggest area of SoC design so SRAM can dominate the performance and total power consumption of SoC design. One of the most effective ways to reduce the total power consumption is scaling down the operating voltage. Conventional 6T SRAM is not suitable for low-voltage region because of read-disturb and half-select disturb. Process and temperature variation also severely degrade the stability of conventional 6T SRAM. This thesis presents a 512Kb low VDDMIN SRAM design with a disturb-free and data-aware write-assist (DAWA) 8T bit-cell. Cross-point structure of this 8T cell can eliminate the half-select disturb and support bit-interleaving structure. Adaptive read/write time tracing replica circuit, ripple bit-line read scheme and local bit-line keeper design enhance read-stability and write-ability. By this DAWA 8T bit-cell and R/W assist scheme, SRAM array can achieve low-voltage operating voltage. A 512Kb test chip is fabricated in UMC 40nm low-power (LP) CMOS process. Post-layout simulation results demonstrate operating frequency of 502.5 MHz at 1.1V and 28.42MHz at 0.6V. The power consumption of read and write operation are 13.5μW/MHz and 6.87 μW/MHz, respectively. The VDDmin of the proposed 512Kb 8T SRAM array is 0.45V.

並列關鍵字

Low VDDMIN SRAM ； Data-aware Write-assist (DAWA) ； Ripple bitline read scheme ； Local bitline keeper ； Adaptive read/write time tracing circuit

參考文獻

Chapter 1

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[1.6] G. Chen, D. Sylvester, D. Blaauw and T. Mudge, "Yield-Driven Near-Threshold SRAM Design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.11, pp.1590-1598, Nov. 2010.

[2.2] J. P. Kulkarni, K. Roy, "Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design," IEEE Transactions on Very Large Scale Integration Systems, 2011.

[2.3] E. Seevinck, F.J. List and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells”, IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp.748-754, 1987.

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實現在40奈米製程技術下可操縱在低操縱電壓的512Kb 8T靜態隨機存取記憶體

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