40 奈米製程技術操縱在低操縱電壓及管線結構的512Kb 8T 靜態隨機存取記憶體

由於現在的3C產品對整個生活週遭影響越來越大，而這些商品一定都需要記憶體來存放資料。而記憶體的存放或是讀取時間也是會影響整個電子產品的在運作上之效率。在靜態隨機存取記憶體裡，因為他跟其他的記憶體相比有較快的處理速度，一般都是放在CPU附近當作快取記憶體，但相較面積之下，確是相對大一些。所以在先進的SoC晶片設計中，靜態隨機存取記憶體往往都是占整個晶片最大的面積。由於這個理由，我們必需好好設計他的操作速度及能量消耗。在一般靜態隨機存取記憶體結構中，主要是以6個電晶體為目前的趨勢。但隨著現在電子業產品的走向，是希望能在越低的操作電壓中運作，使得整個產品耗電量能越少越好，6個電晶體的靜態隨機存取記憶體架構會在低電壓中難以正常操作。故我們設計了一個8個電晶體的靜態隨機存取記憶體能比傳統6個電晶體的靜態隨機存取記憶體操作在更低的電壓，相對來說，也就比較省電能。為了幫助能在低壓下寫入/讀取成功，我們在此40奈米512kb的記憶體中加入了提升字元線的機制以及幫助寫入的電路設計。雖然8個電晶體的靜態隨機存取記憶體原來就比傳統的靜態隨機存取記憶體操作速度快，但還是能夠比其他的記憶體動作快。我們為了提升此8個電晶體的靜態隨機存取記憶體之操作速度，我們運用了漣波位元線讀取架構及管線結構來增進它。

關鍵字

8T 靜態隨機存取記憶體；升壓；管線結構；低操縱電壓；電壓偵測器

並列摘要

As 3C products now growing impact on the entire lives goods must have the memory to store data. Memory storage or read time also will affect the operational efficiency of the entire electronic product. Relatively faster processing speed compared with other memory in the SRAM, which are generally on the CPU as a cache near, but compared to the area that indeed larger some. So in advanced SoC chip design, SRAM area often is the largest in total chip. For this reason, we must have a good design performance and energy consumption. In general SRAM, the 6T structure is current trend. However, with the trend of the electronics industry, which is hoping to operate in a lower working voltage, power consumption can be as little as possible in the entire product. But the 6T SRAM architecture in low voltage is difficult to operate normally. Therefore, we have designed an 8T SRAM than 6T SRAM operating at lower voltage. Relatively speaking, there is more power savings for products. In order to help write/read mechanism achievement, we use the boosting WL mechanism as well as to help write in 40nm 512 Kb memories circuit design. 8T SRAM operating speed is slower than conventional 6T SRAM, but still faster than other memories. In order to enhance our 8T SRAM speed, we use a ripple bit-line and pipeline structure to enhance it.

並列關鍵字

8T SRAM ； boost ； pipeline ； low Vmin ； voltage detector

參考文獻

Chapter 1

[2.2] Harry Pon, "Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications", Solid-State and Integrated Circuit Technology, 2006. ICSICT ’06. 8th International Conference on, pp.697-700, October 2006.

[2.3] Hari Ananthan, Aditya Bansal and Kaushik Roy, "FinFET SRAM – Device and Circuit Design Considerations", Quality Electronic, 2004. Proceedings. 5th International symposium on, pp.511-516, 2004

[2.4] Sherif A. Tawifk, Zhiyu Liu, Volkan Kursun, "Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines For Reduced Area and Enhanced Stability", Microelectronics 2007. ICM 2007. International Conference on,, pp.171-174, December 2007

[2.6] .Adel S. Sdera, Kenneth C. Smith, “Microelectronic Circuits” 6rd ed.

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40 奈米製程技術操縱在低操縱電壓及管線結構的512Kb 8T 靜態隨機存取記憶體

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