支援 4x4 60GHz多輸入多輸出系統之晶格簡化輔助預編碼處理器

Lattice Reduction Aided Precoding Processor for 4x4 60GHz MIMO Systems

藍方君(Fang-Chun Lan)

指導教授 ： 黃元豪

國立清華大學/電機資訊學院/通訊工程研究所/碩士(2012年)

摘要

由於近年來科技蓬勃發展，對於資料傳輸速度以及傳輸品質的要求大幅提升，多輸入多輸出無線通訊系統已經被廣泛的使用。傳統多輸入多輸出天線之預編碼處理器已無法提供可容忍之錯誤率(bit error rate)，因此晶格簡化演算法(lattice reduction)被提出來應用。然而隨著天線數量增加，硬體面積與運算複雜度也大幅度提升。本論文使用改良原始晶格簡化演算法(E-CTLLL algorithm)結合Tomlinson-Harashima預編碼演算法，利用其演算法運算模式跟相關性，考量兩者演算法，可以省略部分額外多餘的運算來降低運算時間跟複雜度。並且兩演算法有許多相同運算方式，故使用運算元件共享來降低硬體面積。此外，本論文所提出來之處理器，在面對不同通道情況變化時，皆可對4x4多輸入多輸出系統執行完整的預先處理(pre-processing)。我們利用TSMC90奈米製程實現本論文所設計之處理器。所設計的處理器可以支援多種操作模式。經由完整驗證流程後，在4x4天線，單純處理Tomlinson-Harashima預編碼的最大固定吞吐量(throughput)為560 M bps(bit per second),結合晶格簡化(當位階輸入為6時)與Tomlinson-Harashima預編碼之處理器的最大固定吞吐量為232 M bps。雖然未能達到60GHz頻段使用的高速資料傳輸速度，但若往後在硬體面積的許可下，本設計的資料傳輸速度將可再提升且有機會實現在實際應用上。

關鍵字

晶格簡化 ； 預編碼 ； 多輸入多輸出系統

並列摘要

The 60GHz band is an excellent choice for wireless applications requiring gigabit-plus data rates, and due to the growing link quality demand of multiple-input multipleoutput (MIMO) wireless communication system, traditional MIMO precodings gradually cannot support enough bit error rate (BER) performance. In addition, lattice
reduction algorithm is proposed to make MIMO precodings achieve the full diversity gain. However, due to the growing number of antennas, the hardware cost and the processing time become a big challenge for hardware design. In this thesis, lattice reduction aided Tomlinson-Harashima precoding algorithm is proposed to get better BER performance than only processing Tomlinson-Harashima precoding. Because both lattice reduction and Tomlinson-Harashima precoding algorithm have several similar operations, the proposed algorithm combines both two algorithms to do the computation sharing and reduce the hardware cost. Furthermore, the proposed algorithm revises some unnecessary operations to reduce the computational complexity by joint consideration of this two algorithms. Moreover, the proposed algorithm supply for different kinds of channel characteristics. The proposed processor can supply several different operating modes. The proposed processor was implemented by TSMC 90nm 1P9M CMOS technology.
According to the synthesis simulation result, the maximum throughput of 4×4 Tomlison-Harashima precoding is 560 M bps(bit per second), the maximum throughput of 4 × 4 lattice reduction (stage number is 6) aided Tomlison-Harashima precoding is 232 M bps.

並列關鍵字

lattice reduction ； precoding ； MIMO system

參考文獻

[2] M. H. M. Costa., “Writing on dirty paper.” IEEE Transactions on Information Theory, vol. 29, no. 3, pp. 439–441, May 1983.

[3] J.-Y. Wang, “Joint QR Decomposition and Lattice Reduction Processor for 8x8 MIMO Systems,” National Tsing Hua University Master Thesis, July 2011.

[4] P.-L. Chiu and Y.-H. Huang, “A scalable MIMO detection architecture with nonsorted multiple-candidate selection,” in Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, may 2009, pp. 689 –692.

[6] C. Windpassinger, “Detection and Precoding for Multiple Input Multiple Output Channels,” Universitat Erlangen-Nurnberg PhD Thesis, June 2001.

[7] C. Peel, B. Hochwald, and A. Swindlehurst, “A vector-perturbation technique for near-capacity multiantenna multiuser communication-part i: channel inversion and