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  • 學位論文

一個十億到一百億赫茲寬頻鎖相迴路

A 1-10 GHz Wide Tuning Range Phase Locked Loop

指導教授 : 朱大舜

摘要


在多數的通訊系統中需要一個本地震盪訊號源作為訊號解調之用,而不同的頻段對應到各種不同的應用,在本論文中提出一個可調頻率範圍為1-10GHz的切換式LC交錯耦合振盪器架構並將其整合於鎖相迴路,預期可以產生出涵蓋L頻段(1~2GHz)、S頻段(2~4GHz)、C頻段(4~8GHz) 、以及X頻段(8~12GHz)的訊號源,根據需求而提供所需的訊號頻率。 論文的第一部分介紹關於寬頻可調範圍震盪器的相關文獻與其架構,由於單一可變電容的可調範圍有限,一基本架構的LC共振腔其可調的頻率範圍也會受限,因此有許多文獻提出各種不同的振盪器以及共振腔架構使其輸出頻率範圍加寬,以及介紹能夠產生雙頻段訊號的共振腔,使得單一振盪器可以有多種應用。 論文的第二部分介紹提出的振盪器架構,使用的架構為多模式切換以達成寬頻輸出的效果,並將會介紹使用的串聯電感架構與工作原理,預期的頻率輸出範圍為1-10GHz;而除頻器的部分則是以串接九級的除二除三單元來達到可除100~1000的寬頻除數範圍,最後再介紹使用的相位頻率偵測器以及電荷泵架構,相位頻率偵測器為傳統的NAND邏輯閘架構;而電荷泵則是採用Current Steering架構;迴路濾波器將以外接在PCB板上面的方式來進行實際量測。 論文的第三部分為各子電路以及鎖相迴路閉迴路的模擬結果,電感的部分使用IE3D電磁模擬軟體來作電感的佈局以及模擬,再使用ADS模擬軟體等效被動元件的電路模型,電路模擬方面則使用Cadence來模擬以及做整個電路的佈局,使用的製程為台積電65奈米製程,操作電壓為1.2V,最後則是根據本次電路設計做個簡單的總結。

並列摘要


A 1-10GHz Wide Tuning Range Phase Locked Loop is proposed in this thesis. In the first part, previous architectures of wide tuning range VCOs are introduced. The tuning range of single varactor is limited, so the frequency tuning range of basic LC-VCO is also limited. Consequently, various wideband VCOs are implemented to increase the frequency tuning range. In the second part the architecture of 1-10GHz Wide Tuning Range VCO is proposed, the expected output frequency is 1-10GHz. The divider is implemented by series of 2/3 cells to achieve the wide division range of 64~1023. Finally the architectures of phase frequency detector and charge pump are introduced. The simulation results are included in the third part, the used process is TSMC 65 nm CMOS technology with 1.2V supply voltage.

參考文獻


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[4] M. Demirkan, S. P. Bruss, and R. R. Spencer, “11.8 GHz CMOS VCO with 62% tuning range using switched coupled inductors,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig. Papers, Jun. 2007, pp. 401–404.
[5] L. Geynet, E. De Foucauld, P. Vincent, and G. Jacquemod, “Fully-integrated multistandard VCOs with switched LC tank and power controlled by body voltage in 130 nm CMOS/SOI,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig. Papers, Jun. 2006, pp. 129–132.
[6] M. Kossel et al., “LC PLL with 1.2-Octave locking range based on mutual-inductance switching in 45-nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 436–449, Feb. 2009.

被引用紀錄


林書羽(2015)。企業主管過度自信與企業技術更新、併購行為關聯性之研究〔碩士論文,國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2015.02245

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