一個應用於生醫系統低功耗多級共用內建截波器之切換式運算放大器三角積分調變器之設計與製作

Design and Implementation of a Power-Efficient Stage-Shared Switched-Opamp ΔΣ Modulator with Built-In Choppers for Biomedical Applications

蕭釧泓(Chuan-Hung Hsiao)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系/碩士(2012年)

摘要

本論文描述一個三階一位元離散時間的三角積分調變器，使用標準0.18-μm互補式金氧半導體製程。切換式運算放大器技術被應用來解決小於一伏特低電壓下MOS開關無法傳遞訊號之問題。使用CRFF架構藉由將輸入訊號直接向前傳遞至量化器輸入端使得各級積分器內的訊號擺幅減小，藉此減少在低電壓下運算互導放大器的規格要求。本論文並提出了一個創新的內建截波器之切換式運算放大器並實現在最前級的積分器內，用來幫助降低放大器內元件不匹配所造成的影響並壓抑1/f雜訊。第二級與第三級積分器共用單一顆運算互導放大器，此多級共用的概念幫助我們減小晶片面積並達到低功耗。
在0.7伏特的工作電壓與256萬赫茲的操作頻率下，此論文所提出的調變器在一萬赫茲的訊號頻寬內，可達到78 dB的信號雜訊及失真比，其中超取樣比為128，以及功率耗損僅有39毫瓦。在這樣的量測結果下得到的FoM為299fJ/conversion-step。總括來說，本論文所提出的多級共用切換式運算放大器之三角積分調變器適合應用於低功耗、高解析度之應用，像是無線可攜式裝置和生醫環境如可攜式、植入式或者甚至拋棄式的醫療產品。

關鍵字

截波穩定 ； 離散時間 ； 切換式放大器 ； 輸入前饋式 ； 低電壓 ； 低功耗 ； 切換式電容電路 ； 三角積分轉換器

並列摘要

This thesis presents a one-bit third-order discrete-time delta-sigma modulator (DT-ΔΣM) using standard 0.18-μm CMOS process. Switched-opamp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of resonators with distributed feedforward (CRFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. A novel chopper-embedded OTA implemented in the first stage effectively eases the impact of component mismatches and suppresses the 1/f noise. The second and third stages share a single OTA. The stage-sharing concept also leads to a smaller die size and a higher power-efficiency.
Operated at 0.7-V supply voltage with 2.56 MHz sampling rate, the proposed modulator achieves 78 dB peak SNDR over a signal bandwidth of 10 kHz with an OSR of 128 and a power dissipation of only 39 μW. The resultant Figure-of-Merit (FoM) is 299 fJ/conversion-step. The proposed SS-SO ΔΣ ADC is suitable for low-power, high-resolution applications like wireless portable devices and bio-signal acquisition.

並列關鍵字

chopper stabilization ； discrete-time ； switched-opamp ； input feedforward ； low voltage ； low power ； switched-capacitor circuit ； delta-sigma (ΔΣ) modulation

參考文獻

[1] J. Goes, N. Paulino, H. Pinto, R. Monteiro, B. Vaz, and A. S. Garcao, “Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12, pp. 2595- 2604, Dec. 2005.

[2] J. Johansson, H. Neubauer, and H. Hauer, “A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications,” in Proc. Eur. Solid-State Circuit Conf., pp. 161-164, Sept. 2003.

[5] F. Cannillo, E. Prefasi, L. Hernandez, E. Pun, F. Yazicioglu, and C. V. Hoof, “1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. Eur. Solid-State Circuit Conf., pp. 267-270, Sept. 2011.

[6] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585-1593, July 2012.

[7] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.