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  • 學位論文

應用於無線測試系統的高面積效率內崁式二進制頻移鍵控發射器之設計

Design of an Area-Efficient Embedded BFSK Transmitter for Wireless Test Systems

指導教授 : 謝志成
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摘要


本篇論文主題為設計一個高面積效率、可內崁於無線測試系統的二進制頻移鍵控 (BFSK) 傳輸器,操作在2.4 GHz並應用於后羿 (HOY)無線測試平台。為了減少使用面積,提出堆疊式的LC架構,應用在數位控制震盪器中。因應所提出的架構,考慮堆疊電感的效應並建立模型,對產生的Q值衰退以及震盪頻率上升現象加以補償,並預測因為電容及電感step改變而造成的頻階變動。此堆疊的電感亦做為on-chip天線使用,利用多路徑傳輸增加天線傳輸功率。此設計亦藉著所提出的switch-Q可變電容以及開放式迴路調變的架構增加資料率。本傳輸器設計經由台積電 (TSMC) 0.18-μm CMOS製成製作量測,並實際達到僅有0.1 mm2的使用面積,以及高達10 Mb/s的傳輸速率,明顯優於其他頻移鍵控傳輸器。此傳輸器與后羿平台做整合,成功達到無線測試之目標。

並列摘要


A design of a binary frequency-shift-keying (BFSK) transmitter for a low area overhead is presented in this thesis. The transmitter is applied to the Hypothesis, Odyssey, and Yield (HOY) wireless test system and operates in the 2.4-GHz industrial, scientific, and medical (ISM) band. To reduce the area overhead, a stacked-LC tank structure is proposed for the digitally-controlled oscillator (DCO). The effects of inductor stacking are modeled and discussed. Compensation is required to account for Q degradation and the oscillation frequency shift. The frequency step is also estimated based on the modified capacitance step and additional inductance step. The stacked inductor also acts as an on-chip antenna using multipath transmission to enhance the emission efficiency. The proposed switch-Q varactor, along with an open-loop modulation architecture, is adopted in order to increase the data rate. The transmitter design is verified through chip fabrication based on a 0.18-μm CMOS process. An area of only 0.1 mm2 and a data rate as high as 10 Mb/s are achieved, which outperforms other FSK transmitters. Integration with the HOY system is also demonstrated.

參考文獻


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