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  • 學位論文

高密度三維通孔電阻式隨機存取記憶體元件之研究

Study of High-density 3D Via Resistive Random Access Memory in Nanoscale CMOS Technologies

指導教授 : 金雅琴

摘要


隨著近年來互聯網相關應用以及手持式電子產品的蓬勃發展,對於內嵌於互補式金氧半導體(CMOS)積體電路之記憶體模組的需求亦是逐年增加。為了應付龐大的數位資訊處理與保存,具有高儲存密度、高可靠度的優勢並且能夠高速寫入/讀取的新興記憶體元件包括相轉式隨機存取記憶體(PCRAM)、磁阻式隨機存取記憶體(MRAM)以及電阻式隨機存取記憶體(RRAM)都具有成為下一世代下非揮發性記憶體(NVM)的潛力。本論文中首先將展示可完全相容於CMOS邏輯製程之鋁後段製程(BEOL)的新型高密度通孔電阻式隨機存取記憶體元件,此一元件可透過簡單的光罩設計製作,除了具備優秀的元件特性外,亦可透過後段製程的連續堆疊來生產三維度儲存陣列以實現超高密度儲存陣列。然而,隨著製程技術不斷微縮並發展至高介電係數金屬閘極(HKMG)互補式金氧半導體先進製程,其後段製程技術中的通孔製造方式從傳統使用的單鑲嵌式演進至雙鑲嵌式,且接點使用的金屬材質亦從銅鋁合金改成銅。此外,為了穩定三維度儲存陣列的操作特性,一個可搭配通孔電阻式隨機存取記憶體元件使用的選擇元件將可堆疊於記憶體元件之上來實現一二極體一電阻(1D1R)的交叉點式儲存陣列。最後,一種新型雙位元通孔電阻式隨機存取記憶體也將於本論文中討論。除了同樣採用先進銅製程進行製造之外,此一元件更具備雙位元儲存能力以及自我整流之特性。以上三種不同的通孔電阻式隨機存取記憶體元件皆具備微小的元件尺寸、容易製造、可三維堆疊、高速切換組態、高阻態比以及優異的可靠度特性等優點,將可望成為下一世代高密度非揮發性記憶體陣列的解決方案之一。

並列摘要


Due to the fast development of internet applications and handheld electronic products, demands of various memory modules in ultra-large scale integration (ULSI) circuits increase every year. For non-volatile data storage applications, emerging memories such as phase change random access memory (PCRAM), magetoresistive random access memory (MRAM) and resistive random access memory (RRAM) were investigated. These next-generation nonvolatile memories (NVM) have the advantages of high storage density, excellent reliability and high write/read speed. In this dissertation, a new high-density via RRAM which is fully compatible with aluminum-based complimentary metal-oxide-silicon (CMOS) logic back-end-of-line (BEOL) process are proposed and studied first. This device can be easily implemented through special design in the single mask layer layout. This device exhibits excellent electrical characteristics and has the feature to achieve ultra-high storage density array in a repeatable pattern in standard BEOL layers. As CMOS technologies push forward, the fabrication method of via in BEOL evolves from the traditional single-damascene method to dual-damascene method and the material of via also change from aluminum to copper. In addition, a back-end selector, which compatible with this copper-based via RRAM, is developed to be stacked above the via RRAM to achieve 1D1R cross-point memory array, making 3D-stackable memory array possible. Finally, a novel twin-bit via RRAM is also demonstrated in this dissertation. The novel memory cell not only can be fabricated in advanced copper-based technology, but also enable the capacity of two bits storage and self-rectifying characteristic. These different via RRAMs all possess advantages such as small cell size, CMOS compatibility, 3D stacking ability, high switching speed, good reliability. Therefore, via RRAM is expected to become available solution for next-generation high-density NVM.

並列關鍵字

CMOS NVM BEOL RRAM

參考文獻


Chapter 1
[3] M. R. Ouellette, D. L. Anand, and P. Jakobsen, “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy,” in IEEE 2001 Customintegrated Circuits Conf., May 2001, pp. 191-194.
[7] Y. Choi, I. Song, M.-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. G. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y.-J. Lee, Q. Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y.-T. Lee, J. Yoo, and G. Jeong, “A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, Feb. 2012, pp. 46-48.
[11] S. G. Narendra, Laura C. Fujino, and Kenneth C. Smith, “Through the Looking Glass— The 2015 Edition: Trends in Solid-state Circuits from ISSCC,” Solid-State Circuits Magazine, IEEE, vol. 7, no. 1, pp.14-24, 2015.
[12] S.-M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M.-S. Song, K.-H. Kim, J.-S. Lim and K. Kim, “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” in Electron Devices Meeting (IEDM), 2006 IEEE International, Dec. 2006, pp. 1-4.

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