基於單元分組的超導節能磁性FPGA標準單元配置算法

A Novel Placement Algorithm for Superconducting Energy Efficient Magnetic FPGA

薩加(Vayalapalli, Sagar)

指導教授 ： 陳博現 ； 何宗易 教授

國立清華大學/電機資訊學院/電機工程學系所/碩士(2020年)

摘要

FPGA是一種可讓使用者編寫程式的數位裝置，並能夠提供數位電路有效且靈活的實現。
FPGA由配置邏輯塊組成且被路由網路包圍與限制在I/O腳的區域中。
FPGA為許多不同傳統半導體製的應用提供了一個價格更低的解決方案。
隨著單通量量子(SFQ)技術發展迅速，使用SFQ技術的FPGA將變得非常的有用。
先前的研究著重介紹了第一個高效能使用磁性SFQ技術的FPGA，這個FPGA有望以高頻低能耗的狀態下運行。
在這個論文中，我們提出一個全新的布局演算法，不同於CMOS製的FPGA，高效能磁性RSFQ的FPGA能夠滿足所有SFQ的限制。
我們準確地研究了RSFQ FPGA布局與布線問題，並且開發出了一套新穎的針對超導體FPGA的布局演算法，這個演算法旨在利用減少相連的邏輯塊的距離以最小化整體的布局面積與切換盒的擁擠狀況。
這個演算法的主要屬性是「單元分組」、「全域布局」與「細部布局」，目的是在符合超導電子與RSFQ的限制下提供一個最佳的合法布局結果。
我們將我們的布局結果與基準系統的結果進行比較，成功的減少成本(HPWL)約27%及布局區域大約20%。

關鍵字

FPGA

並列摘要

FPGAs are user-programmable digital devices that provide efficient, yet flexible, implementations of digital circuits. FPGAs consist of configurational logic blocks surrounded by routing network and bounded on a grid by I/O pins. FPGAs provide a significantly cheaper solution for various applications of traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA will be very useful. Prior research highlights a first energy-efficient magnetic SFQ specific FPGA which promises to operate at very high frequency with low power dissipation. In this paper, we propose a new innovative placement algorithm Energy Efficient magnetic RSFQ FPGA complying all the SFQ constraints in the design unlike CMOS FPGAs. We have explored placement and routing problems in RSFQ FPGA precisely and developed a novel Placement Algorithm for Superconducting FPGA which aims to minimize overall placement area and congestion on switch boxes by reducing distance between connected logic blocks. The main attributes of the algorithm are - Cell Grouping, Global Placement and Detailed Placement which aims to provide best legal placement solution complying all the rules of Superconducting Electronics and RSFQ constraints. We compared our placement results with a baseline system and were able to reduce cost (HPWL) and placement area approximately by 27% and 20% respectively.

並列關鍵字

FPGA ； SFQ ； RSFQ ； CAD ； EDA

參考文獻

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