用於潛在時依性介電崩潰測試之較精確且高壓即時電容監視電路

A More Accurate and High Voltage Real-time Capacitor Monitor Circuit for Potential TDDB Testing

周宗興(Tsung-Hsing Chou)

指導教授 ： 張彌彰

國立清華大學/電機資訊學院/電子工程研究所/碩士(2013年)

摘要

隨著製程不斷演進，導線寬度以及導線和導線間的距離縮小。而導線間的距離降低會增加介電值中金屬導線間的電場。因此時間相依介電質崩潰的研究和解決是必要的。在電路完全崩潰之前發現有漏電流的增加，稱之為軟式崩潰。這段時間，等效電容值可能出現了變化。但軟式崩潰時，沒有個好的量測方法。
楊學姊提出了四顆電晶體差動振盪器[1]，是個擁有高敏感度之即時電容偵測電路。藉由米勒效應，電容值變化造成頻率變化之變化量被放大。但無法藉由此方式得知絕對電容值。此外，希望能用高電壓，以較短的時間觀察軟式崩潰，但製程發展過程可能無法取得抗高壓電晶體(I/O)。本論文中將會研究考慮製程變異的精確電容量測方法，以及做出使用核心(core)電晶體用以更高電容跨壓的電路。
為了精確量測，本論文提出斜率逼近法，藉由外部參考電容消除製程變異。外接電容連接至差動對輸出的雙端。待測電容的接法也相同除了兩端為傳輸閘所控制。如果合適的設計傳輸閘，可使兩者的斜率值非常的逼近。藉由使用兩個或以上外接參考電容可提供參考斜率值。以及在軟式崩潰時，量測待測電容的週期差。可利用參考斜率以及量測週期差來找出電容差值。
此電路設計基於台積電65奈米製程。使用核心電晶體之電路可提供兩倍跨壓於待測電容且沒有閘極氧化層過壓。電路包含改良差動對、兩種附屬電路、疊接核心傳輸閘以及它的控制電路。
若把高壓電晶體納入考量，共有五種監視電路。為了便於觀測，敏感度應該要高。為了精確量測，兩電容之斜率誤差應該要小。最後，在五個變異模擬情況下，選出(敏感度/斜率誤差)最高者為最好架構。

關鍵字

時依性介電崩潰 ； 閘極氧化層過壓 ； 電容監視電路

並列摘要

The interconnect line width and spacing shrink with advanced technology. The reduction in line space increases the electric field in the dielectric between metal lines. Thus, time dependent dielectric breakdown (TDDB) needs to be investigated and resolved before the technology is fully qualified. Before the dielectric is completely breakdown, leakage current has been observed to increase (soft breakdown). During this time, the interconnect capacitance (Cmom) might have been changed. But, there is no good way of measuring the capacitance during soft breakdown.
Yang has proposed a 4T differential ring oscillator as a real time capacitor monitor circuit [1] with high sensitivity. It magnifies the oscillation frequency change due to capacitance change with Miller effect. But the absolute capacitance is unknown using this method. Besides, it is desirable to observe soft breakdown in shorter time by higher voltage stress, but the I/O MOSFET might be unavailable while technology is in development. An accurate capacitance measurements method under process variation and higher voltage stress using core MOSFET circuit are presented in this thesis.
For accurate measurement, the slope matching method is proposed to eliminate process variation using external reference capacitors (Cext). The Cext is connected to the output ports of differential pair. And the Cmom is connected in the same except with additional transmission gates on both ends. The slopes (dT/dC) for Cmom and Cext should be very close to each other if transmission gate is properly designed. Using two or more external reference capacitors provide reference slope (ΔTCext/ΔCext). And ΔTCmom is measured during TDDB soft-breakdown. ThusΔCmom is found by reference slope and measured ΔTCmom.
The circuit design is based on TSMC 65LP technology. The core MOSFET based monitor circuit provides higher (2xVDD) stress on the target capacitor without gate oxide overstress. The circuit consists of proposed differential pair, two types of peripheral circuit, cascode core transmission gate and its control circuit.
If the I/O MOSFET is taken into consideration, there are five types of monitor circuit. For easy observation, the sensitivity should be high. For accurate measurement, the slope offset of Cmom/Cext should be small. In the end, the best type of monitor circuit is chosen with highest (sensitivity/slope offset) under five corner simulations.

並列關鍵字

TDDB ； gate oxide overstress ； capacitor monitor circuit

參考文獻

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Chen, Zhe; Prasad, K.; Chaoyong Li; Ning Jiang; Gui, Dong, "Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects," IEEE Transactions on Device and Materials Reliability, vol.5, no.1, pp.133,141, March 2005

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