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  • 學位論文

提出3D-IC與系統封裝設計之快速模擬軟體的新架構

Proposing A New Fast 3D Electromagnetic-based RLC Extraction Software Platform for 3D-IC and System-in-Package Designs

指導教授 : 張克正
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摘要


隨著產品所需的執行頻率來到數十億赫茲階層,電阻、電容、電感等寄生參數對三維晶片(3D-IC)及系統級封裝(System in Package, SiP)的影響也越來越大。過去我們應用在封裝、印刷電路板、超大型積體電路設計或無線電頻上的設計方法學大多是採用夾心帶線(stripline)或是微帶線(microstrip)等結構,對三維晶片及系統級封裝的設計的幫助有限。有鑑於此,為解決三維晶片與系統封裝設計上傳輸線問題,我們提出一套快速模擬三維晶片與系統封裝設計上傳輸線的軟體新架構。 過去,因為產品所需的執行頻率較低,所以SiP中用來連接系統內各個元件的金屬線可以被視為完美的聯接線,不會有延遲及干擾的產生。隨著頻率越來越高,我們必須將系統級封裝中的金屬聯接線視為傳輸線(Transmission line)。 因此,傳輸線所衍生出關於訊號完整度(signal integrity)的種種問題,例如:延遲(RC delay)、基底耦合(substrate coupling)、串音(crosstalk)、阻抗匹配(impedance match)、電磁干擾(Electromagnetic Interference, EMI)、信號反彈(reflection)等問題都需要在設計流程中更精確模擬計算,並且去了解、量化這些傳輸線所衍生出訊號完整度問題。 本篇論文將會利用三維的電磁模擬軟體,對三維晶片及系統級封裝進行電感、電容與電阻的分析,設計出一套快速抽取電阻、電容、電感值的軟體架構並觀察各種寄生效應對電路的影響,進而量化三維晶片及系統級封裝上的種種訊號完整度問題。 我們將提出一個整合性高、速度快、能夠輕易的學習使用的電性模型軟體,來協助使用者,希望藉此提高產品良率,降低設計迴圈,並且更能準確模擬並維持信號完整度及電源供應完整度的問題,以求對三維晶片及系統級封裝產業上有更大的貢獻。

並列摘要


The trend of advanced 3D IC and system-in-package (SiP) designs is toward gigahertz-level operating frequencies and very compact form factors. Leveraging the design methodologies of packaging, PCB board, VLSI, or RF, is not practical during advanced 3D IC or SiP designs because those methodologies assume the availability of microstrips and striplines, which are rarely available to the designers of 3D IC or SiP. Therefore, interconnect problems on 3D-IC and system-in-package mandate a new design software platform that can address the needs of high-performance 3D IC and SiP designers. In the low frequency design, metal connections between different components can be thought as perfect connections which will not affect the performance. However, the requirement for high frequency product has become a trend now. Those connections used in the package should be modeled as transmission line. Therefore, those issues of signal integrity such as RC delay, IR drop, substrate coupling, crosstalk, impedance match, Electromagnetic Interference, reflection … etc on 3D IC and system-in-package need to be modeled accurately and be taken into account in the design flow so that simulation and modeling of these interconnections have become more and more important. It is important to quantify these values and need more researches for better understanding them. We’ll use 3 dimensional field solvers to analyze the basic electrical properties of 3D IC and system-in-package in this thesis. Then we’ll design a fast 3D electromagnetic-based RLC Extraction Software Structure and observe the real behavior of the circuit, and we quantified the signal integrity problems on 3D IC and system-in-package. We’ll provide an accurate and user-friendly simulation software advanced interconnect modeling software (AIMS) to help designers to increase the design productivity, to minimize the design cycle, and to maintain the signal integrity and power integrity in this thesis. We can give suggestions to the designers on how to achieve better signal integrity in high-speed 3D-IC and SiP system-in-package.

參考文獻


[5] K.-J. Chang, et al., “HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs,” Hewlett-Packard Company, Palo Alto, CA 94304, USA, 1991.
[6] C. Huang, “A New Verification Strategy to Rigorously Test Two Pieces of Electromagnetic Field Simulation Software,” Master Thesis, NTHU, 2007.
[8] L.-F. Chang, et al., “In-depth Speed and Accuracy Comparison of Inductance Extraction for SoC Signal Integrity and Tool Integration,” 2002.
[11] RAPHAEL User’s Manual, Version 2003.09, 2003.
[13] K. S. Oh, et al., “Capacitance Computations in a Multi-layered Dielectric Medium Using the Closed-form Spatial Green’s Functions,” IEEE Trans, 1994.

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