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  • 學位論文

氮化鎵及氮化銦鎵金氧半電晶體製作

Fabrication of U-GaN and InGaN MOSFETs

指導教授 : 黃智方

摘要


此篇論文研究使用矽離子當作汲、源極摻雜的氮化鎵金氧半電晶體。為了保持在離子佈植時的活化率同時避免表面氮的跑掉,我們發現最佳的活化製程為在氮氣中使用快速熱退火於1200度5分鐘。此時所量測出最低的片電阻為62Ω/ohm。另一項研究為使用原子氣相沉積,沉積氧化鋁當作閘極介電層,為避免氧化鋁在高溫燒結時會有裂解,必須先做燒結後才能沉積閘極介電層。最後,當完成的元件經過混合氣體的燒結後可以有效改善氧化層-氮化鎵的界面,其最佳的導通電阻為24 Ω*cm以及電流密度大於10 mA/mm。 我們另外的研究為氮化銦鎵/氮化鎵材料,在研究中發現,即使活化溫度達到1100度,由於汲、源極仍然未完全活化,使得最大導通電流密度大約1mA/mm,這些元件存在著很大的汲極漏電流,乃為由基板漏電流造成。

並列摘要


This thesis investigates the fabrication of GaN MOSFETs utilizing Si as the implant species for the source and drain regions. In order to prevent nitrogen loss from the surface while keep ion implantation activation efficiency, we find the best annealing process is to perform RTA at 1200 ℃ for 5 minutes in N2 ambient. The measured sheet resistance is as low as 62Ω/ohm. We investigated the performance of ALD deposited Al2O3 as the gate dielectric. To prevent Al2O3 being recrystallized during high temperature annealing, the ohmic contacts are formed before gate oxide deposition. The devices are forming gas annealed to further improve the oxide-GaN interface. The best measured RON is 24 Ω*cm and the current density above 10 mA/mm. We also studied MOSFETs using InGaN/GaN material system. It is found that even the activation temperature is as high as 1100 ℃, the ION(max) is only about 1mA/mm due to poor activation in the source and drain. These devices exhibit significant drain leakage current which is attributed to substrate leakage current.

並列關鍵字

GaN InGaN activation MOSFETs

參考文獻


[1] F. Ren, M. Hong, S. N. G. Chu,,M. A. Marcus, M. J. Schurman, A. Baca, S. J. Pearton and C. R. Abernathy,“Effect of temperature on Ga2O3(Gd2O3)/GaN metal–oxide–semiconductor field-effect transistors,” Applied Physics Letters, vol.73, NUMBER 26,PP.3893-3895,1998.
[4] K. Matocha, T.P. Chow, and R.J. Gutmann, ” High-Voltage Accumulation-Mode Lateral RESURF GaN MOSFETs on SiC Substrate” ISPSD April 14-17 ,2003..
[5] Kevin Matocha,T.Paul Chow and and Ronald J. Gutmann , “High -Voltage Normally Off GaN MOSFETs on Sapphire Substrates” IEEE Transactions on Electron Devices, vol. 52, no. 1, January 2005
[6] W. Huang, T. Khan, and T. P. Chow, “Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates.” IEEE Electron Device Letters,vol.27,no. 10, October 2006.
[7] Takehiko Nomura,Hiroshi Kambayashi,Yuki Niiyama Shinya Otomo and Seikoh Yoshida, “High-temperature enhancement mode operation of n-channel GaN MOSFETs on sapphire substrates.” Solid-State Electronics, 52 pp.150–155, 2008.

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