在三維晶片中考慮串擾的情況下的矽穿孔通道緩衝器插入方法

Crosstalk-aware TSV Buffer Insertion in 3D IC

黃柏晨

指導教授 ： 黃婷婷

國立清華大學/電機資訊學院/資訊工程學系/碩士(2014年)

摘要

三維晶片整合是減緩線路延遲的前瞻技術。實作三維晶片的方式是整合二維晶片和矽穿孔通道。為了提升三維晶片的良率，矽穿孔通道集結成束成為矽穿孔通道區。遺憾的是，在三維晶片中，在矽穿孔通道區的串擾耦合雜訊會造成顯著的時序降解。傳統上，調整緩衝器尺寸是個有效率的方法去解決時序問題。然而，我們觀察到在三維情況下，矽穿孔通道在增加攻擊者的緩衝器尺寸造成的時序降解會比二維的線路更為嚴重。在這篇論文中，我們推導出受害者矽穿孔通道在不同攻擊者矽穿孔通道緩衝器尺寸下的延遲模型。基於以上的觀察和矽穿孔通道延遲模型，我們提議在平面規劃之後以整數線性規畫為基礎的緩衝器插入方式。我們實驗結果顯示在平面規劃之後，在時序限制下，我們的方法相較於貪婪方法可以降低6.66%的緩衝器面積。

關鍵字

三維晶片 ； 矽穿孔通道 ； 串擾 ； 緩衝器插入

並列摘要

3D integration is one of the promising technology to alleviate interconnection delay. Implementing 3D IC is to integrate 2D ICs with through-silicon vias (TSVs). For yield consideration, TSVs are bundled together as a TSV block. Regrettably, this placement results in crosstalk coupling noise in TSV block which may cause significant timing degradation. Traditionally, buffer sizing is one of the effective methods to solve the problem of timing. However, we observe that the increase of buffer size of aggressor TSV will cause more serious timing degradation to victim TSV in 3D than wires in 2D case. In this paper, we develop a delay model of a victim TSV surrounded by aggressor TSVs with different size of driving buffers. Based on the TSV delay model, we propose an ILP based buffer insertion method after floorplan stage. Our experimental results show that our proposed method can reduce 6.66% buffer area in average under timing constraint after floorplan stage as compared with a greedy method.

並列關鍵字

3D IC ； TSV ； Crosstalk ； Buffer insertion

參考文獻

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