- 學位論文
應用於多核心處理器之交易層級內嵌式追蹤器設計
Design of Transaction-Level Embedded Tracer for Many-Core Processors
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延伸閱讀
- 蔡冠群 (2013). 用於多核心系統晶片交易層級內嵌式追蹤器架構 [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-1402201415091198
- Ho, Y. J. (2008). 內嵌式數位訊號處理器之偵錯追蹤技術 [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-0903200911354336
- Chou, W. T. (2011). 在嵌入式多核心平台上設計並實作具移植性的高效能核心間溝通函式庫 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2011.01442
- 鄧紀賓（2002）。適用於內嵌式數位訊號處理器模組設計〔碩士論文，元智大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0009-0112200611293527
- Wu, P. W. (2008). An Integrated Multimedia Framework for Embedded Dual-core Processors [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-2002201314574330