考慮重分配階層繞線之三維積體電路測試排程方法研究

3D IC Test Scheduling with Re-Distribution Layer Routing Considered

粘丞勛(Cheng-Hsun Nien)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

摘要

中文摘要
隨著積體電路製程技術的不斷進步，核心電路基底的系統單晶片設計已經成為積體電路設計的主流。而在一個核心電路基底的系統單晶片設計裡，包含許多核心電路，包括了處理器、記憶體、數位矽智財、類比訊號模組、混合訊號模組等。這些核心電路各自擁有獨立的測試，然而隨著在IC設計越來越複雜，如何有效地測試整體電路成為IC設計的過程中一項困難的挑戰，因此測試介面(test wrapper)可再使用測試存取的優點，大大增加核心電路在測試應用中的靈活性。在此篇論文，我們發現核心電路測試介面輸出入腳位TAM BUS連線個數與核心電路的測試時間，是一個trade-off的關係，假使透過減少分配核心電路測試介面輸出入個數的連線，雖然可以紓解繞線擁擠的情況，但卻會增加該核心電路的測試時間，反之，如果增加TAM BUS分配到核心電路測試介面輸出入腳位的連線個數，則會加重繞線擁擠的情況，但卻可以減少該核心電路的測試時間。在本篇論文，我們討論在三維積體電路測試架構之下，並考慮在繞線擁擠限制下，結合測試排程、重分配階層繞線以及分配測試介面個數，最小化整體測試時間方法之研究。我們的方法首次考慮繞線擁擠的情況下，做測試排程，比起既有的研究，我們的方法更有效地分配連線並減少測試時間。

關鍵字

三圍積體電路SoC測試排程 ； 測試介面 ； 重分配階層繞線

並列摘要

Abstract
As the process technology continues to progress, core-based system-on-chip (SoC) has become the mainstream of VLSI circuit design. A core-based SoC design contains many embedded cores, which may be processor, memory, digital IPs, analogy signal modules and mixed-signal modules. As the IC design becomes more complex, the reduction of the test application time has become an important concern. These embedded cores have their own dedicated tests. Therefore, test wrappers are required to enable both core reuse and easy test access.
In this thesis, we find that there is a trade-off relation between the test time of an embedded core and the number of pins of test wrapper as well as TAM Bus wires. We can relieve the routing congestion by reducing the number of pins of test wrapper and TAM Bus wires but the test time of core will become more longer and vice versa. In this thesis, we minimize the test application time by test scheduling for three Dimensional Integrated Circuits with re-distribution layer routing considered. Our approach is the first work that performs the simultaneous test scheduling with re-distribution layer routing congestion considered.

並列關鍵字

3D-IC test scheduling ； test wrapper ； re-distribution Layer

參考文獻

[1] E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test” in Proc. Int. Test Conf., pp. 911-920, 2000.

[2] G.L. Craig, C.R. Kime, and K.K. Saluja, “Test Scheduling and Control for VLSI Built-in Self-Test,” IEEE Trans Computers, vol. 37, no. 9, pp. 1099-1109, 1988.

[3] E.J. Marinissen, R. Arendsen, G. Bas, H. Dingemanse, M. Lousberg, and C. Wouters, “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores” in Proc. Int. Test Conf., pp. 284-292, 1998.

[4] P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips” in Proc. Int. Test Conf., pp. 294-302, 1998

[5] Lee Whetsel, “Addressable Test Ports: An Approach to Testing Embedded Cores” in Proc. Int. Test Conf., pp.1055-1064, 1999