有限產能下之投料模式構建與應用之研究--以半導體測試廠為例

An Input Model for a Semiconductor Final Test Facility

邱俊智(Chun-Chih Chun)

指導教授 ： 王孔政

中原大學/工學院/工業工程研究所/碩士(2001年)

https://doi.org/10.6840/cycu200100343

摘要

在半導體產業中，大部分的文獻都在探討有關上游晶圓廠的投料方式，本文主要是探討半導體中下游的封裝與測試整合廠中，依據測試廠的產能限制，構建出一套投料模式，期望使固定週期內的投料產品與投料數量，並利用演算法求出可以同時滿足封裝廠與測試廠產能之投料組合。同時利用程式模擬與實際驗證之方式，來證明所構建之投料模式，比工廠的現行投料作業較佳的績效。
在相關產能的限制條件之下，其投料模式必須滿足公司之期望目標，如下列三點：
1. 使封裝廠與測試廠之總收益增加；
2. 使產出數量滿足顧客需求量之要求；
3. 減少生產線上的WIP，縮短產品製成時間。
本研究第一部份說明研究背景、現況與問題描述。第二部份為投料方式與基因演算法相關文獻之探討。第三部份將問題轉化為基因演算法求解模式，依據程式執行後所求出之投料組合，實際應用於投料作業上，並與過去之投料模式作產能利用率、產品製造週期時間、產出量、與在製品數量等之變異數分析，檢驗新的投料模式對產能及產出量之影響是否顯著。最後為後續研究計畫與期望成果。

關鍵字

半導體 ； 封裝測試 ； 投料模式 ； 有限產能 ； 基因演算法 ； 產能規劃

並列摘要

In the semiconductor Industry, most of literatures discussed the input model of wafer fabrication. This thesis discussed the input model of the assembly and final test combined facility. It’s based on the assumption of capacity of final test facility to develop a suitable input model. We use the result to measure system performance from the proposed input model.
Base on the test capacity constrained, we use genetic algorithms for find device input optimization solutions. To archive the expected goal of facility, this input model must solve below 3 points:
1. Make the maximum profit both Assembly and Final Test Facility.
2. Make good output performance to satisfy customer demand.
3. Reduce WIP quantity and cycle time.
The first part of this thesis is about the background of research and problem defined. The second part is the relevant literature of genetic algorithm. And the latest part is use GA program to find the optimum solution. Finally, we use the result doing the Analysis of Variance to get more evidence to prove this input model is more usefully than the one we use before.

並列關鍵字

Input Model ； Genetic Algorithm ； Limited Capacity ； Capacity Planning ； Semiconductor ； Assembly and Final Test

參考文獻

Andersson M., Olsson G., “A Simulation based decision support approach for operational capacity planning in a customer order driven assembly line.” Proceedings of the 1998 Winter Simulation Conference. pp. 935-941, 1998.

Chung S. H., Huang H. W., “The Design of Production Activity Control Policy for Wafer Fabrication Factories.” Journal of the Chinese Institute of Industrial Engineers, Vol. 16, No.1, pp. 93-113, 1999.

Classey C. R., Resende M. G.. C., “Closed-Loop Release Control for VLSI Circuit Manufacturing.” IEEE Transactions on Semiconductor Manufacturing. Vol. 1, No.1, pp. 36-46, 1988

Freed T., Leachman R. C., “Scheduling Semiconductor Device Test Operations on Multihead Testers.” IEEE Transactions on Semiconductor Manufacturing, Vol. 12, No. 4, pp. 523-530, 1999.

Levitt M. E., Abraham J. A., “Just-in-Time Methods for Semiconductor Manufacturing,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 3-9, 1990.