佈局規劃階段之電源分佈網路的設計與最佳化系統

隨著製程技術的進步，尤其在進入深次微米製程後，電子遷移和電壓衰減的問題，對於高效能晶片設計的可靠度之影響就變得更加的重要。因此，電源分佈網路之設計及最佳化，便成為一個重要的研究課題。然而，在實體佈局階段，元件置放和細部繞線完成後，要修正電源分佈網路是一件非常費時且消耗人力的工作。所以為了要避免於實體佈局階段與佈局結果分析之間反覆的修改與驗證，電源分佈網路應該於早期的佈局規劃階段進行規劃。在本篇論文裡，我們將進行一個以佈局規劃為基礎的電源網路模型及設計最佳化方法。若將本文所提出之方法與以往提出的方法做比較，最主要的差別在於本文提出了一個有系統的方法去建立一個初始可行的電源分佈網路，此網路對晶片提供了一個穩定且符合電壓衰減要求的電壓，接下來再利用模擬進化方法反覆的分析與驗證來改進電源分佈網路所使用的繞線資源。我們最佳化的目標是在電流密度與電壓衰減的限制條件下，使用最小的繞線資源。最後的實驗結果顯示出我們所提出的方法可以使用較少的繞線資源建構一個穩定而有效的電源分佈網路。本文所提出的演算法已用C程式語言實現，並可與商用電腦輔助設計軟體設計流程整合。

關鍵字

佈局規劃；電壓衰減；電子遷移

並列摘要

As the process technology enters the deep sub-micron design era, electromigration and voltage drop issues become more crucial for reliable and high performance ASIC designs. However, it is very expensive to fix the power distribution network after the detailed layout composition is completed. In order to avoid the iterations including placement and routing, the power distribution network should be accurately planned at the post-floorplan stage. In this thesis, we will study design methodology of floorplan-based power distribution network. Compared with other approaches, the main distinction of our approach is that it presents a systematic method to build an initial feasible power distribution network such that excellent voltage regulation in the power demand across the chip is achieved. Then, by iteratively improving the power distribution network based on simulated evolution, our optimization goal is to minimize the wiring resources under current density and voltage drop constraints. Experimental data shows that the proposed approach can construct robust power distribution networks with fewer routing areas. The proposed algorithm has been implemented in a C program and integrated with commercially available tools in existing ASIC design flow.

並列關鍵字

voltage drop ； floorplan ； electromigration

參考文獻

[1]. Dahal, L. Lev, and S. Mitra, “Design of an Efficient Power Distribution Network for the UltraSparc Microprocessor”, in the Proc. of ICCD, pp. 118—123, 1995.

[4]. H-J. Rothermel and D.A. Mlynski, “Computation of Power and Ground Supply Nets in VLSI Layout”, Proc. of 18th Design Automation Conference, pp. 37-42, 1981.

[9]. S. Chowdhury and M.A. Breuer, “Optimum Design of IC Power/Ground Nets Subject to Reliability Constraints”, IEEE Trans. on Computer Aided Design, pp. 787-796, 1988.

[11]. Dharchoudhury, A.; Panda, R.; Blaauw, D.; Vaidyanathan, R.; Tutuianu, B.; Bearden, D. “Design and analysis of power distribution networks in PowerPCTM microprocessors “Design Automation Conference, 1998. Proceedings , 1998

[12]. Takashi Mitsuhashi and Emest S. Kuh, “Power and Ground Network Topology Optimization for Cell-Based VLSIs”, Proc. of 29th Design Automation Conference, pp. 524-527, 1992.

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佈局規劃階段之電源分佈網路的設計與最佳化系統

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