中文摘要 本篇論文的主要目的在於討論如何設計與製作一部DSP-CPLD數位電路發展系統。經由實際的驗證與模擬,證明本套實驗設備確實可以改善數位邏輯電路教學,同時縮短學習DSP-CPLD的時間,引領學習者快速進入晶片設計的世界。 在本論文裡,我們將DSP系統加到由本實驗室[5]所研發出來的LP2900的CPLD數位邏輯實驗器上。加入DSP時,我們確保其相容性,讓原來能夠在LP2900上面做的實驗,都能夠正確的動作,如此一來,原來購買LP2900的學校或公司團體,能夠再添購DSP實驗模組來運行DSP實驗以及DSP-CPLD實驗。 DSP-CPLD邏輯實驗器包含的主題為:(1)DSP與DSK硬體的學習、(2)DSP組合語言與C語言的撰寫、(3)DSP數位訊號的處理、(4) DSP類比晶片的驅動、(5)中斷處理、(6)Memory Interface與Peripheral Interface、(7)CPLD硬體學習、(8)VHDL程式的撰寫、(9)DSP與CPLD溝通軟體的撰寫、(10)DSP與CPLD的硬體結合架構與設計。 關鍵字:DSP、TMS320C54XX、TLC320AD50C、Texas Instruments、CPLD,VHDL,ALTERA,數位電路發展系統、數位訊號處理、數位訊號處理器。
ABSTRACT The objective of this thesis is to implement a DSP-CPLD digital logic design system. Through practical verification and simulation, it is proved that this experimental equipment can improve digital logic circuit teaching, and shorten the time of learning CPLD. By the aid of manufacturing-academic cooperation, this equipment is being manufactured on line. At present, the complete product is on the market. In this thesis, we include the DSP system inside the LP2900 CPLD digital logic design system, which is designed by our laboratory [5] . The DSP processor can effectively coordinate with the LP2900, consequently, all the CPLD experiments can be easily extended to our new system. The experiment subject of DSP-CPLD digital logic design system include: (1) DSP and DSK hardware study. (2)DSP assembler language and C language. (3)DSP digital signal process. (4)Drive DSP analog chip. (5)DSP interrupt process. (6)Memory Interface and peripheral interface. (7)CPLD hardware study. (8)VHDL language (9)DSP and CPLD software communicate. (10)DSP and CPLD hardware combine and design. Keywords: DSP, TMS320C54XX, TLC320AD50C, Texas Instruments, CPLD, VHDL, ALTERA, Digital Logic Design System