IC封裝製程之模流與金線偏移分析

打線接合(Wire Bonding)與覆晶接合(Flip Chip，FC)皆為目前電子封裝中主要的電路聯線技術之一，可使IC晶片與封裝基板或導線架完成電路的聯線以發揮電子訊號傳遞的功能；目前IC元件朝向輕薄短小的趨勢發展，其輸出/入(I/O)數逐漸增加，而傳統使用打線接合的IC因I/O接點限制在晶片周圍，在不增加晶片的面積之下，I/O數的增加勢必使得金線之間距縮小，因此金線偏移問題對於成品良率的影響將更為重要。而隨著電子產品朝向高速化、多功能、高可靠度、低成本以及輕薄短小的趨勢演進之下，I/O數的增加使得周列式(Peripheral Array)的打線接合技術逐漸不敷應用，屬於面陣列式(Area Array)的覆晶接合技術正可滿足此需求，但由於晶片與基板間的熱膨脹係數差異頗大，在組裝過程中易因熱循環產生熱應力集中而造成元件的破壞，因此，可藉由在兩者之間的間隙填充環氧樹脂以減少熱膨脹係數的差異來提高元件封裝的可靠性；目前以利用毛細力作為充填驅動力的填膠方式為主，但其充填時間長且過程易產生缺陷，因此，如何改善充填製程及縮短製程時間來提高生產效能是覆晶封裝技術發展的關鍵之一。本文針對兩種IC封裝形式－球腳格狀陣列(Ball Grid Array，BGA)與覆晶封裝進行研究；第一部份利用電腦輔助工程(CAE)軟體模擬IC封裝之轉移成型製程的充填過程，探討融膠流動行為並進行金線偏移分析，將之與實驗結果進行比較與驗證；第二部份則依不同製程參數，如間隙高度、凸塊間距與凸塊配置等建立模型進行底部充填實驗，並利用CAE軟體進行模擬分析，將兩者之結果進行比較與驗證。

關鍵字

模流分析；覆晶封裝；電腦輔助工程分析； IC封裝；金線偏移

並列摘要

Wire bonding and flip chip are the main interconnecting technology of electric packages. They interconnect IC chips with substrate or leadframe to transfer electric signals. Nowadays, the trend of IC device is toward lighter, thinner, smaller and the I/O counts are increasing. Due to the I/O joints of wire-bonding IC are restricted around the chip and I/O counts are increasing, the distances between wires become much closer. Therefore, the influence of wire sweep becomes more critical on products. Since the trend of electric products is toward high speed, multifunction, high reliability and low cost, the periphery-array wire-bonding technology may be insufficient due to the increasing of I/O counts. The area-array flip-chip technology can meet the requirement. However, due to the coefficient of thermal expansion mismatch between the chip and substrate, the solder joints will experience fatigue strains during temperature cycling and lead to electrical failure. Therefore, filling the gaps between chips and substrate with encapsulant can increase the reliability. Nowadays, underfill process of flip chip driven by capillary force is the main filling method. However, the underfill flow is very slow and could be incomplete or result in voids. Therefore, it is critical for flip-chip to speed up the filling process and avoid the defects. Two kinds of IC packages, Ball Grid Array (BGA) and Flip Chip, are studied in this paper. In first section, CAE software is used to simulate the filling process during transfer molding and predict the wire-sweep deformation. In the second section, the underfill experiments of different process conditions such as gap height, bump pitch, and bump patterns are proceeded; moreover, the CAE software is used to simulate the experiments. Furthermore, the simulated results are used to verify the experimental results.

並列關鍵字

CAE ； Mold-Flow Analysis ； Flip Chip ； Wire Sweep ； IC Encapsulation

參考文獻

[6] Y. R. Chen, “Mold-Flow Simulation and Wire Sweep in IC Encapsulation”, Master Thesis, Chung Yuan Christian University, July 2001.

[8] Y. L. Chen, “The Analysis and Optimization of Wire Sweep in IC Encapsulation”, Master Thesis, Chung Yuan Christian University, June 1997.

[9] C. H. Chang, “Mold-Flow Analysis of High-Density IC Encapsulation”, Master Thesis, Chung Yuan Christian University, August 2002.

[2] L. T. Nguyen and F. J. Lim, “Wire Sweep during Molding of Integrated Circuits”, in IEEE 40th ECTC, Vol. 1 pp.777-785, 1990.

[3] S. Han and K. K. Wang, “A Study on Wire Sweep in Encapsulation of Semiconductor Chips Using Simulated Experiments”, Transactions of the ASME, Vol. 117, pp. 178-184, September 1995.

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IC封裝製程之模流與金線偏移分析

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