高密度IC封裝之模流分析

Mold-Flow Analysis of High-Density IC Encapsulation

張千惠(Chien-Huei Chang)

指導教授 ： 鍾文仁

中原大學/工學院/機械工程研究所/碩士(2002年)

https://doi.org/10.6840/cycu200200595

摘要

隨著IC塑膠封裝朝著輕、薄、短、小的趨勢演進，欲在小的體積內擠進為數眾多的內引腳勢必要將腳間距縮小，金線與金線間的距離將愈形緊密，因此金線偏移對成品不良率的影響將更加重要。尤其在新世代的構裝技術中，BGA的腳數發展已突破400以上，金線偏移的影響更鉅，亦是當前IC封裝業界亟需克服的問題。但隨著IC元件功能日益強大，打線接合(Wire Bonding)方式已漸漸不敷應用，取而代之的是以凸塊取代金線作為晶片與基板接合的覆晶接合技術；雖然覆晶封裝優勢在高性能高I/O的元件，然而由於晶片與基板的熱膨脹係數差異頗大，在組裝過程中，易因熱循環產生熱應力集中，造成元件的破壞；為了減少熱應力的產生，在晶片與基板中充填封裝材料，以減少晶片與基板之熱膨脹係數差異，由於利用毛細力做為充填驅動力，充填時間相當長，且充填過程易產生缺陷，因此，如何提高覆晶封裝元件的可靠度、改善充填品質及縮短製程時間、提高生產效能是覆晶封裝技術發展的主要關鍵。
本文針對兩種高密度IC封裝形式－覆晶(flip-chip)及球狀陣列(BGA)封裝進行研究。第一部份利用CAE分析軟體模擬覆晶底部充填製程，討論不同幾何條件、製程參數、材料性質及分析模型對充填之影響；第二部份則分別利用2.5D及3D分析模型模擬IC封裝之轉移成型製程中融膠流動行為並進行金線偏移分析，且結合實際充填及金線偏移之結果以相互比較驗證。

關鍵字

金線偏移 ； CAE ； 3D模流分析 ； IC封裝 ； 毛細力 ； 模流分析 ； 底部充填 ； 覆晶封裝

並列摘要

Wire bonding technology is the most common bonding method for IC package. Because the type of IC package is toward lighter, thinner, and smaller and the functions of chip are more powerful, the numbers of connectors are increasing. The distances between wires become much closer because the smaller volume needs to contain more connectors. Therefore, the influence of wire sweep becomes more critical in high-density packages.
Nowadays, with the numbers of I/O increasing, the wire bonding method may be insufficient and the solder bumps of flip chips can replace the wires as connectors. However, due to the coefficient of thermal expansion mismatch between the chip and substrate, the solder joints will experience fatigue strains during temperature cycling and lead to electrical failure. This problem can be significantly reduced by filling the remaining gaps between chip and substrate with encapsulant. However, the underfill flow is very slow and could be incomplete or result in voids. Therefore, it is critical for flip-chip technology to speed up the encapsulation process and avoid the defects.
Two kinds of high-density IC packages, flip chips and BGA, are studied in this paper. The influences of geometrical dimensions, process conditions, and material properties etc. on underfill are discussed in the first section. In the second section, the 3D and 2.5D analytic models are used to simulate the flow during transfer molding and predict the wire-sweep deformation. Furthermore, the experimental results are used to verify the simulated results.

並列關鍵字

CAE ； IC package ； 3D molding simulation ； Flip-chip ； CAE molding analysis ； wire sweep ； capillary ； dispensing ； underfill

參考文獻

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[4] W. H. Leong and M. K. Schwiebert, “Underfill Flow as Viscous Flow Between Parallel Plates Driven by Capillary Action”, IEEE Transactions on Components, Packaging, and Manufacturing Technology Part C, Vol. 19, No. 2, pp.133-137, April 1996.

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