本論文提出一種可擴充的排序電路架構,此電路利用奇偶傳遞排序法(Odd-Even Transposition Sort)的規律性,將排序電路模組化,使用硬體描述語言設計出可擴充的排序電路基本模組,藉由組合任意數量的基本模組,可完成能排序任何輸入資料數量的排序電路,此排序電路能應用在如FlexRay需要排序資料的通訊系統中。FlexRay是一種高速傳輸、時間觸發且具容錯能力的車載網路通訊協定,本論文以硬體描述語言設計FlexRay的通訊控制器(Communication Controller)電路,在通訊控制器電路中,需要使用依數值大小排序資料的功能且輸入數值資料數在固定筆數內,基於電路重複使用及關閉無用基本模組之構想,我們設計一個適用於通訊控制器的排序電路以符合上述之要求,並可依排序資料數量調整運作模組的數量,以節省能源。最後將通訊控制器電路進行模擬與合成,驗證其功能,最後在FlexRay進行節點互通的實驗,以證明設計出的通訊控制器電路與排序電路是能正常運作的。
In our thesis, we propose an extensible sorting hardware architecture circuit. Analyzing the repetition of the Odd-Even Transposition Sort method, we design a basic sorting cell by the hardware description language. We can apply several basic sorting cells to build as the extensible sorting hardware circuit and satisfy the required input numbers of the sorting data. The extensible sorting hardware circuit can be applied to the FlexRay communication controller circuit for adjustment of the several cases of the sorting input data numbers. FlexRay is a specification of vehicle network communication which provides high speed, timing trigger, and fault tolerance. In our thesis, we also implement the circuit of the FlexRay communication controller with the Verilog hardware description language. We demand a sorting circuit to sort the timing table data in the communication controller circuit to correct the global time. The basic sorting cell circuit can be re-used and convenient to other applications. The sorting circuit has a function to save energy by turning off the not-use modules. Finally, we verify the circuit of communication controller to simulate and synthesize the circuit on the FPGA. We experiment the field try to confirm our design of the communications controller and extensible sorting circuit working correctly.