高精確度及面積效益的固定長度布爾乘法器

High-accuracy and Area-efficiency Fixed-width Booth Multiplier

劉偉羿(Wei-Yi Liou)

指導教授 ： 陳元賀

中原大學/工學院/資訊工程研究所/碩士(2015年)

https://doi.org/10.6840/cycu201500079

摘要

布爾乘法器(Booth Multiplier)廣泛的應用在各種超大型積體電路(VLSI)的設計中，然而乘法器是運算單元的主要元件，對架構的面積和運算速度有相當大的影響。因此，對布爾乘法器進行研究，提出面積更小，速度更快又滿足精確度要求的架構有很好的研究意義。 本研究開發了固定長度布爾乘法器的動態誤差補償電路的高精確度基於條件概率和計算機模擬。系統的解決方案基於條件概率和期望值的生成，利用計算機模擬和具有最高精確度的解決方案。所提出的方案除了是高精確度，也減少面積效益和提高功率效率。本研究中使用的TSMC 0.18-um CMOS製程的16位元布爾乘法器，運行速度達到100MHz和消耗功率為6.7mW。

關鍵字

固定長度乘法器 ； 超大型積體電路

並列摘要

Booth Multipliers are widely used in the design of various kinds of VLSI, while multiplier is the main component of arithmetic logic units(ALU), having a great effect on the area of architecture and instruction cycle.Therefore, it has a significant sense to make a research of the Booth multiplier and proposes an accurate architecture with lower area and higher speed.This paper developed a dynamic error-compensation circuit for fixed-width Booth multipliers of high accuracy based on probability and computer simulation . the proposed begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed approach is area-effective and power-efficient. This study used the TSMC 0.18-um CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

並列關鍵字

Booth Multipliers ； VLSI

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