高精確度固定長度Booth乘法器的超大型積體電路實現及其離散餘弦變換的應用

Booth乘法器(Booth Multiplier)廣泛地應用在各種超大型積體電路（VLSI）的設計中。隨著科技與應用需求的發展，單顆晶片集成了更多的功能，而乘法器往往是運算單元中主要的元件，對架構的面積跟運算速度的影響舉足輕重。因此，對Booth乘法器進行研究，提出面積更小，速度更快，同時又滿足精度要求的架構，具有很好的研究意義。這篇論文，基於條件概率對固定長度Booth乘法器進行研究，提出了誤差補償電路的兩種設計方案。方案一採用Booth編碼器的條件概率，而方案二則採用輸入系列的條件概率。與當前主流的設計方案比較，提出的方案具有面積小，速度快，精度高的優點，另外，無需耗時的電腦模擬過程，補償電路易於實現。兩個設計方案採用台積電(TSMC) 0.18-μm CMOS制程進行實作：運用方案一設計的16位元乘法器運行速度達到100MHz，功率消耗是1.6mW；基於方案二設計的32位元乘法器在實作基礎上下線製造，晶片運行速度到達50MHz，功率消耗是7.3mW。另外，為了呈現效果，將方案二的Booth乘法器運用在2D-DCT架構中並下線製造，跟採用傳統的乘法器比較，減小了面積開銷而信噪比(SNR)只降低了2dB。

關鍵字

數學概率模型；動態誤差補償；固定長度Booth乘法器

並列摘要

Booth Multipliers are widely used in the design of various kinds of VLSI. With the development of science and technology and application requirements, a single chip integrates more functions, while multiplier is the main component of arithmetic logic units (ALU), having a great effect on the area of architecture and instruction cycle. Therefore, it has a significant sense to make a research of the Booth multiplier and proposes an accurate architecture with lower area and higher speed. This paper makes a study of fixed-width Booth multiplier based on the conditional-probability and proposes two design approaches of error-compensated circuit. The first approach uses conditional-probability of the Booth encoder and the second approach uses the conditional-probability of input series. The proposed designs achieve high accuracy with low area and high speed comparison with of existing design approaches in the literature. In addition, the compensated circuit is facile without exhaustive simulation. These two proposed designs were implemented using the TSMC 0.18-μm CMOS process. The 16-bit multiplier of the first approach operates at a frequency of 100 MHz with power consumption of 1.6 mW. Based on the second approach, the proposed 32-bit multiplier has an operation frequency of 50 MHz with power consumption of 7.3 mW. Furthermore, to present the effect, Booth multiplier of the second approach can be applied into the architecture of 2D-DCT. Compared with the traditional Booth multiplier’ applications, the proposed 2D-DCT cores can reduce area cost with the penalty of only 2 dB signal-to-noise ratio (SNR).

並列關鍵字

mathematical probable model ； fixed-width Booth multiplier ； dynamic error-compensation

參考文獻

[1] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.

[2] S. C. Hsia and S. H. Wang, “Shift-register-based data transposition for cost-effective discrete cosine transform,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 15, no. 6, pp. 725–728, Jun. 2007.

[3] H. Y. Lee and I. C. Park, “Balanced binary-tree decomposition for area-efficient pipelined FFT processing,” IEEE Trans. Circuits Syst. I, vol. 54, no. 4, pp. 889–900, Apr. 2007.

[5] C. Y. Li, Y. H. Chen, T. Y. Chang, L. Y. Deng, and K. W. To, “Period extension and randomness enhancement using high-throughput reseeding-mixing PRNG,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2011, to be published.

[8] A. G. M. Strollo, N. Petra, and D. DeCaro, “Dual-tree error compensation for high performance fixed-width multipliers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 8, pp. 501–507, Aug. 2005.

國際替代計量

高精確度固定長度Booth乘法器的超大型積體電路實現及其離散餘弦變換的應用

全文下載

主題瀏覽