可靠度導向之洩漏功率最小化的方法

Reliability Oriented Multiple-Vth Assignment for Leakage Power Reduction

吳世偉(Shih-Wei Wu)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/碩士(2008年)

https://doi.org/10.6840/cycu200900362

摘要

隨著製程進入深次微米後，在低功率設計中，次臨界洩漏電流所造成的功率消耗成為重要的議題，而雙臨界電壓元件置換為降低洩漏電流功率的其中一種方法，本論文對此方法提出一個快速有效率的演算法，提出了以層次為單位的置換方法，增加元件置換的效率，然而隨著製程的下降，負偏壓溫度不穩定效應造成元件老化(延遲時間增加)的問題也日益嚴重，所以電路的可靠度問題也成為重要的議題，即電路的使用年限，而且由於電路中不同的元件會有不同的老化速率，因此不同電路在相同的時序預留空間下，會有部份電路無法達到所規定的使用年限，因此我們利用不同臨界電壓元件擁有不同的元件延遲時間特性，提出了使用三種元件資料庫的置換方法，即可靠度導向的多重臨界電壓置換，用來改善電路的洩漏功率且同時改善電路的可靠度，而我們的演算法擁有下列兩點的特色：
(1)有效的權重定義，使得改善電路使用年限後，仍能擁有不錯的洩漏功率改善。
(2) 提出層次為基礎的置換方法，加快洩漏功率最佳化的速度。
　　最後經由實驗結果，我們可以在5%的時序預留空間下，讓電路都能達到相同的使用年限10年，並得到不錯的洩漏功率改善，平均為52.8%。

關鍵字

洩漏電流 ； 雙臨界電壓元件置換 ； 負偏壓溫度不穩定效應 ； 時序預留空間

並列摘要

As process technology scales to nano-meter, the leakage power dissipation has become an important concern for low power design in VLSI. Dual threshold voltage assignment is a popular effective technique to reduce leakage power. In this paper, we propose novel efficient algorithm to deal with this problem. We develop a level-based algorithm to decrease the time spent by high threshold voltage assignment. In addition to leakage power reduction, circuit reliability is another important issue with technology process scaling down, because the negative bias temperature instability (NBTI) of PMOS device becomes serious as gate oxide become thinner. The NBTI leads to threshold voltage degradation of PMOS over a period of months or years such that cell delay increase over a period of months or years. Therefore, the circuit will have timing violation after a long time operation. In order to deal with this problem, designer normally leave timing margin to ensure that there is no timing violation in the circuit after a long period of time. Nonetheless, different circuits still have different lifetime under the same timing margin. In order to deal with this problem, we also propose reliability oriented multiple-Vth assignment algorithm. Our algorithm has the following two important features:
(1)Due to the effective weight definition, we still can greatly save the leakage power consumption after circuit reliability improvement.
(2)Due to level-based assignment, we can decrease much time spent by high threshold voltage assignment.
　　Finally, the results show that our algorithm can extend circuit lifetime to 10 years for all circuit under 5% timing margin and save 52.8% leakage power in average.

並列關鍵字

leakage current ； dual vth assignment ； negative bias temperature instability ； timing margin.

參考文獻

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