降低測試功率之可測試設計與最小漏電流向量產生技術

A DfT and Minimum Leakage Pattern Generation Technique for Test Power Reduction

高瑋聰(Wei-Chung Kao)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.00001

摘要

本文提出最小漏電流向量產生器以及可測試性技術設計，用來降低在移位模式下的靜態測試功率。此技術將最小漏電流向量產生的問題轉換成虛擬布林函數最佳化問題，而漏電流的非線性任務函數被近似成線性函數使得此問題可以有效的以現行的虛擬布林函數最佳化軟體來求解。並提出一個電路分割方法以減少總CPU運算時間。低靜態功率可測試性設計架構在移位模式下用來給予最小漏電流向量。在ISCAS’89的基準電路使用TSMC90奈米製程的實驗顯示，在有限的最佳化時間內小電路在不作電路分割下靜態功率降低最多到32.7%。大電路可以降低靜態功率從8.3% (不分割電路)到17.47%(分割成64份電路下)。此外，最佳化的時間可以從3,600秒(不分割電路)降低至83秒(分割成64份電路下)。此技術降低靜態功率並不需改變製程或資料單元設計，此技術的缺點會有些微的面積增加以及效能減低。

關鍵字

可測試設計 ； 測試 ； 低功率 ； 靜態功率 ； 漏電流

並列摘要

This thesis presents a minimum leakage pattern generator and a DfT technique to reduce static test power during shift mode for nanometer technology. This technique transforms the minimum leakage pattern generation problem into a pseudo Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by existing PBO solver. A partition method is applied to reduce the overall CPU time. The proposed DfT structure for low static power can be used to apply the minimum leakage pattern during shift mode. Experimental results on ISCAS’89 benchmark circuits using TSMC 90nm technology show that under the limited optimization time the static power is reduced by up to 32.7% for small circuits without partition. For large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3,600 seconds (without partition) to 83 seconds (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cell design. The penalty of this technique is small area overhead and performance degradation.

並列關鍵字

DfT ； testing ； low power ； static power ； leakage

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