應用於智慧物聯網模組之類比數位轉換器關鍵佈局技術研究

近年來，隨著科技的進步無線網路的應用已十分普及，隨著行動裝置的發展，物聯網的發展也更加盛行，對於無線傳輸模組需求也與日俱增，且無線網絡傳輸速率也不斷提高。其中類比數位轉換器的速度與精準度便會決定無線傳輸模組的效能，IC佈局設計對於信號傳輸速度影響很大，因此IC佈局設計為本論文的重要課題。本論文設計係以10-bit SAR ADC為核心，其架構由自舉式開關、電容陣列、位移暫存器、SAR邏輯電路以及比較器組成，本論文佈局的實現則是利用垂直線對稱中心式的電容佈局及反向器佈局等效電路佈局，並遵循電容匹配原則佈局的方式來做快速佈線，並得以利用工具來做模擬，時時修正細節，以確保電容呈現比例關系，能夠達到高精度的匹配程度，更期能融合各項成熟技術，在未來開發出更優越的精密儀器。經驗證後與先前文獻所提出的方法相比較，可發現本論文的設計實際得以執行且使電容具有一致性匹配，每個輸出端的寄生電容皆為1.29947fF，且不會產生額外的寄生電容，同時使得信號不會受到雜訊、電容或電感的干擾。本論文之目的是對IC佈局最佳化做了許多改良，係實現即使沒有校正電路的情況下也能兼顧高速及高解析度的ADC，在積體電路實現上，發現當電壓差值 Vinp – Vinn 趨近於0時會出現一個非線性的轉換情形。

關鍵字

SAR類比數位轉換器；智慧物聯網；高解析度ADC

並列摘要

Recently, with the advance of science the wireless networks are popular. With the development of mobile devices and the Internet of Things (IoT) more prevalent than ever, the requirements for wireless module have increased day by day and wireless network transmission rate increases The speed and accuracy of analog to digital converters will determine the performance of wireless modules. IC design has had a great impact on the follow-up of signal transfer speed, therefore, Therefore, the development of the IC Design Rules becomes the major target in this study. This study design was based 10-bit SAR ADC. This architecture consists of bootstrapped switches, capacitor arrays, shifting registers, SAR logic circuits, and comparator. This study follow capacitance matching principium, this study can quickly layout in tool and simulate the result and also do detail change make sure the accurate of capacitor ratio. It is hope that the result of this study can be higher capacitance matching degree, and integrates every mature technology to develop more superior precise instrument in the future. The study results show that the proposed system yields comparable and better measurement accuracy compared to previous approaches. The findings from the study also confirm its practical feasibility and Make the capacitor have consistent matching. The parasitic capacitance of each output terminal is 1.29947fF as well as no more additional parasitic capacitance. Furthermore, the response was not affected by the interferences such as noise, capacitance, inductance. The purpose of this study is to improvements have been made to optimize the IC layout, in order to achieve even if there is no correction circuit. In this case, high-speed and high-resolution ADC design can also be taken into consideration. Index Terms: mobile devices, wireless module, differential signals, Successive approximation analog to digital converter.