1.5伏特演算式類比數位轉換器的設計與製作

The Design and Implementation of 1.5V Algorithmic Analog-to-Digital Converter

黃建國(Chien-Kuo Huang)

指導教授 ： 呂啟彰

國立虎尾科技大學/電機資訊學院/電機工程研究所/碩士(2010年)

摘要

近年來，由於可攜性系統的廣泛應用，造成操作在低電源電壓下的電路需求逐漸增加，例如:感測裝置、生醫應用。本論文以低電壓低功率為考量，使用雙重取樣的技術設計一個8-Bit以及轉換速率為2MHz之演算式類比數位轉換器，並在取樣保持電路的設計上使用米勒電容效應的方法，此技術在取樣模式與保持模式下提供兩種不同的等效電容值，使得電路的取樣速度與精確度皆可以得到改善。
在本論文中，整體電路包含了取樣保持電路、次類比數位轉換器、次數位類比轉換器、解碼器、暫存器、脈波產生器以及多工器。本研究使用TSMC 0.35um 2P4M的製程進行設計與製作，根據模擬結果，在電源電壓為1.5V下，輸入電壓範圍為±0.5V，整體之功率消耗約為8.2mW。

關鍵字

演算式類比數位轉換器 ； 米勒電容式取樣保持電路

並列摘要

In recent years, the portability systems become popular. It makes the demand for low voltage and low power circuit increased, such as sensor devices and bio-medical applications. The aim of this thesis is to investigate the design techniques of algorithmic ADC for low voltage and low power applications. The target architecture is an algorithmic ADC with the double-sampling technique. The resolution and the conversion rate is 8-bit and 2MHz respectively. Furthermore, Miller-capacitance effect method is used to the front-end sample-and-hold (S/H) circuit. It has two different capacitance values during the sampling phase and hold phase, making the circuit speed and accuracy of sampling are to be improved.
The algorithmic ADC consists of the sample-and-hold circuit, sub-ADCs, sub-DACs, decoders, clock generator and multiplexers. In this research, the algorithmic ADC with double-sampling technique has been designed in standard TSMC 0.35um CMOS 2P4M process. Simulation results show that under the 1.5V power supply and the input range of ±0.5V, and the estimated power dissipation is about 8.2mW.

並列關鍵字

Algorithmic ADC ； Miller-capacitance-based S/H circuit

參考文獻

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