12位元100 MHz電流式數位類比轉換器之設計與實現

Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter

侯宗典(Tsung-Tien Hou)

指導教授 ： 陳朝烈 ； 黃俊岳

崑山科技大學/工程學院/電子工程研究所/碩士(2006年)

https://doi.org/10.6828/KSU.2006.00005

摘要

本論文中利用TSMC 0.35-um 2P4M mixed signal的製程來實現一個12位元高速電流式數位類比轉換器，其取樣頻率為100 MHz，此電流式數位類比轉換器是利用分段電流模式(segmented current mode)的架構來實現，此架構由七個高有效位元(7 MSBs)轉換成127個相同的電流源和五個低有效位元(5 LSBs)轉換成二進位加權方式的電流源所組成，利用此架構可改善數位類比轉換器的微分非線性誤差(DNL)、突波(glitch)和確保電路單調性。
在電路模擬方面，我們利用HSPICE來進行模擬，對於12位元 100 MHz電流式數位類比轉換器的模擬結果如下：積分非線性誤差(INL)<±0.3 LSB，微分非線性誤差(DNL)<±0.25 LSB，穩定時間(settling time)等於9 ns，突波為5.8 pV-s。當輸入頻率為1 MHz與49 MHz之正弦波時，無突波動態範圍(SFDR)分別為80 dB與67 dB，電路的消耗功率為127 mW。
在量測方面，對於取樣頻率為100 MHz之數位類比轉換器量測結果為積分非線性誤差(INL)<±0.6 LSB，微分非線性誤差(DNL)<±0.4 LSB，穩定時間(settling time)等於10 ns，突波為25 pV-s。當輸入頻率為200 kHz與5 MHz之正弦波時無突波動態範圍(SFDR)分別為70.3 dB與63.51 dB，電路的消耗功率為142 mW。

關鍵字

12位元 ； 電流式數位類比轉換器 ； 數位類比轉換器

並列摘要

In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture.
The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.3 LSB, DNL is less than 0.25 LSB, settling time is 9 ns, and glitch is 5.8 pV-s. For 1MHz sine wave input and 100 MHz sampling rate, the SFDR is 80 dB, and for 49MHz sine wave input and 100 MHz sampling rate, the SFDR is 67 dB. The power consumption is 127 mW at the maximum conversion rate.
The real world measurement results show that the proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.6 LSB, DNL is less than 0.4 LSB, settling time is 10 ns, and glitch energy is 25 pV-s. For 200 kHz sine wave input and 100 MHz sampling rate, the measured SFDR is 70.3 dB, and for 5 MHz sine wave input and 100 MHz sampling rate, the measured SFDR is 63.51 dB. The measured power consumption is 142 mW at the maximum conversion rate.

並列關鍵字

12-bit ； DAC ； digital-to-analog converter ； current-steering DAC

參考文獻

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