1.5伏特十位元管線式類比數位轉換器

隨著影像處理與通訊系統的快速發展，高解析度的類比數位轉換器常被應用在這些前端接收路徑之中，另一方面近年來個人可攜式電子產品的成長，對於類比數位轉換器的功率消耗需求越來越嚴苛，所以在解析度和功率消耗的考量下，眾多種類的高速類比數位轉換器架構當中，管線式類比數位轉換器是一個很好的選擇。管線式類比數位轉換器擁有速度快、解析度高及功率消耗低的優點，因此能達到高速的輸入性能和快速的處理能力。在本論文中，將針對管線式類比數位轉換器做設計，並在前端取樣保持電路的設計上使用米勒電容效應的方法，此技術在取樣模式與保持模式下提供兩種不同的等效電容值，使得電路的取樣速度與精確度皆可以得到改善。在論文中，使用TSMC 0.35um 2P4M的製程，實現一個電源電壓為1.5V，取樣頻率為20MHz的十位元管線式類比數位轉換器，根據佈局後模擬結果，輸入電壓範圍為±0.5V，整體電路工作於371.09375KHz的輸入訊號頻率下可得到SNDR為52dB，功率消耗約為32mW，電路佈局面積為2276×2072um2。

關鍵字

管線式類比數位轉換器；米勒電容式取樣保持電路

並列摘要

With the fast growth of video process and communication systems, high-resolution analog-to-digital converters (ADCs) are required in the front-end received path. In recent years, the growth of portable consumer electronics, power dissipation is becoming an increasingly important design issue in analog-to-digital converters. In many types of high-speed analog-to-digital converter (ADC) architectures, a pipelined ADC architecture has become an attractive choice. Pipelined ADC has the advantages of high-speed, high-resolution and low power dissipation, and therefore it can achieve good dynamic range performances and fast throughput. This thesis focuses on designing the pipelined ADC. Furthermore, Miller-capacitance effect method is used to the front-end sample-and-hold (S/H) circuit. It has two different capacitance values at the sampling phase and hold phase. Miller-capacitance-based S/H circuit can be employed to relax the requirements for the first pipeline stage. In this thesis, a 10-bits 20MHz pipelined ADC implemented using the TSMC 0.35um CMOS process with a 1.5V power supply. In the result of post-simulation, this design achives a signal-to-noise and distortion ratio (SNDR) of 52dB at an input signal frequency of 371.09375KHz and an input range of ±0.5V that estimated power dissipation is about 32mW. The layout area is about 2276×2072um2.