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  • 學位論文

氮化鈦成長條件對嵌入式動態隨機存取記憶體之影響

The effects of TiN Growth for the Embedded Dynamic Random Access Memory

指導教授 : 鄭慧愷

摘要


本文是從氮化鈦(TiN)作為嵌入式動態存取記憶體(Embedded DRAM)之電容層為基礎,探討成長氮化鈦(TiN)薄膜的過程中,藉由改變製程的溫度和製程氣體之流量,觀察最後各預設的實驗條件下,薄膜的成長狀況。接著,以薄膜的成長結果與晶圓的良率做連結,設定漏電流(Leakage Current)為晶格良率的測定標的,觀察其上下電極氮化鈦(TiN)的生長條件改變,對晶圓的品質與良率(yield)所造成之影響。 在實驗設計方面,採用田口玄一博士(Dr. Taguchi Genichi)於1980年代推廣的田口式L9直交表(Taguchi Orthogonal Arrays)來配置實驗參數,收斂實驗的進行次數,取晶圓製造過程中的相關變數TiCl4流量、NH3流量、Ar流量和溫度來進行交叉實驗。以原本製程溫度400℃為基礎,設定實驗溫度分別從410、430到450℃,每增加20℃為一個實驗區間,共需執行九次的成長實驗。以橢圓偏光儀(Ellipsometer)和電子探針式(Chip Probe)的晶圓可靠度測試機台WAT(Wafer Acceptance Test Tool)來測量,並將漏電流設定為檢測晶圓良率之測定標的,並根據晶圓之膜厚分布圖與漏電流的相關性,證實影響晶圓良率的重要因子為反應的溫度。實驗結果顯示,當製程溫度在430℃時,晶圓漏電流的表現最佳,有良率數目最大值。此外,在此反應溫度下,除了膜厚均勻度與電阻率最佳,也有著最小的漏電流和最大的晶圓良率。

並列摘要


In this thesis, we discussed how the TiN electrode's deposition in a capacitor layer of conditions in embedded DRAM changed under different reaction temperatures and gas flows. Furthermore, using leakage current as our measurement, we explored how TiN electrodes’ deposition quality affect wafer’s yield. Our experiment adapted Taguchi Orthogonal Arrays which popularized by Dr. Taguchi Genichi in 1980s' to converge our experiment trials with 4 variable factors: TiCl4 flow、NH3 flow、Ar flow, and temperature. Each gas flow had 3 different settings and the deposition temperature set with 20℃ interval and exclusive lower bound at 400℃(410℃, 430℃, and 450℃)for a total of 9 converged experiments. Outcomes of experiments were collected with Wafer Acceptance Test Tool (WAT) that equipped with Ellipsometer and Chip Probe. Based on the correlation between leakage current and film thickness of wafer, we hypothesis that the only significant factor affecting wafer’s yield to be the reaction temperature. Our experiment results showed that wafer reached the minimize leakage current and maximum number of die yield; when the process temperature were set at 430℃. In addition, this reaction temperature resulted in optimized film, uniformity and resistance.

參考文獻


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