考慮晶片變異之多重功率模式緩衝器合成

On-chip-variation-aware Power-mode-aware Buffer Synthesis

李豫(Yu Lee)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700392

摘要

隨著製程科技的進步，系統晶片中的元件尺寸越來越小，在目前的積體電路設計上，常使用多重電壓模式( Multi-power mode )下去運作一晶片已達到節省功率的消耗，在此篇論文中，我們考慮到了在電壓不同的情況下會造成不同的製程變異( On-Chip-Variation )，而電壓越小製程變異越大，反之，電壓越大製程變異越小，我們提出使用在兩種電壓下的感知緩衝器，讓製程變異在不同的電壓下所造成的時序差異( Clock Skew )可以獲得改善。
此兩電壓的感知緩衝器分成前後兩個，是用來優化多重電壓下的時序差異以及有資料傳遞的兩條路徑的時序差異，前面的感知緩衝器會使用較小的電壓下去運作用來做粗略的調整，後面的感知緩衝器會使用較大的電壓去運作用來優化較細部的時序差異，會使用動態選擇的方式，讓不同電壓下可以選擇不同的通道，我們使用混合整數線性規劃法(Mixed Integer Linear Programming, MILP)來找出兩電壓感知緩衝器內部的緩衝器數量配製，並使時序差異逼近於0。

關鍵字

多重電壓模式 ； 製程變異 ； 兩電壓感知緩衝器 ； 時序差異

並列摘要

As the process technology continues to progress, the size of technology node continues to shrink. The use of multiple power modes is a widely used technique to save power consumption. In this thesis, we consider on-chip-variation (OCV) issue in a multi-power mode design. Note that, in a multi-power-mode design, minimizing clock skew becomes more difficult. Especially, the voltage gets lower, the OCV gets higher. We propose a Two-Stage Power Mode Aware Buffer (PMAB) structure to minimize the clock skew in different voltage modes with considering OCV effects. The PMAB structure is composed of two PMAB in two different voltages. We use a Mixed Linear Programing algorithm to determine the number of buffers to be inserted in each PMAB channel. Experimental shows that using our algorithm can make circuit reach almost zero skew.

並列關鍵字

Multi voltage mode ； On-Chip-Variation ； Two-Stage Power Mode Aware Buffer ； Clock skew

參考文獻

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