晶片網路架構上之高利用率動態緩衝器配置方法

系統晶片(System-on-Chip)設計已經廣泛地運用在現今多媒體、電信、消費型電子領域的電路設計。隨著製程不斷地縮小，越多的矽智財(IP)可以整合到單一晶片裡。各個矽智財之間的訊息交換將成為系統效能的瓶頸。一個基於封包交換傳輸方式的晶片網路(Network-on-chip)被提出來克服解決系統晶片連結的問題。在晶片網路架構中，路由器(router)是最基礎的元件，路由器設計主宰著所有晶片網路的功能與特性。其中在路由器設計中，對網路效能極具影響力的是緩衝器資源。然而在實際的應用當中，傳統的設計會造成緩衝器使用不平均和利用度降低。在本篇論文中，我們將介紹一個新穎的動態緩衝器配置方法用在我們所提出的路由器架構，我們的架構藉由分散緩衝器達到分享緩衝器的目標。此外我們克服了單一緩衝器路由器的缺點並且有效的利用緩衝器資源。研究結果顯示我們可以使用60%的緩衝器達到與傳統架構的晶片網路相同的效能。

關鍵字

晶片網路；路由器架構；緩衝器配置

並列摘要

System-on-chip design has been commonly used in modern circuit design in multimedia, telecommunications and consumer electronics domain. With the technology scales down, more IP cores can be integrated into a single ship. The interconnection between IP becomes the performance bottleneck. Network-on-chip (NoC) which is packet switch based communication is proposed to overcome the SoC interconnection problem. The NoC router (or so-called switch) is the fundamental component in NoC architecture, all the functionality and property of NoC is dominated by the router design. The most influence to network performance in router design is the buffer resource. However, under real application the buffer usage will be unbalanced and utilized inefficiently. In this thesis, we introduce a novel dynamic buffer allocating method with our router architecture organized by separate buffers to achieve shared buffer purpose. Moreover, we conquer the shortcoming of single buffer router and utilize the buffer resource efficiently. Experimental results show that we can achieve the same performance of conventional architecture in NoC while using only 60% buffer size.

並列關鍵字

Network-on-chip ； router architecture ； buffer allocation

參考文獻

[1] L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, vol. 35, pp. 70-78, 2002.

[2] H. Jingcao and R. Marculescu, "Application-specific buffer space allocation for networks-on-chip router design," in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 354-361.

[3] C. Xuning and P. Li-Shiuan, "Leakage power modeling and optimization in interconnection networks," in Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on, 2003, pp. 90-95.

[4] T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 524-529.

[6] W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Design Automation Conference, 2001. Proceedings, 2001, pp. 684-689.

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晶片網路架構上之高利用率動態緩衝器配置方法

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