在二維網格晶片中旁繞式輸出緩衝區之高效能行列路由器

Detour Output Buffer of High-Performance RoCo Decoupled Router for Network-on-Chip

黃柏舜(Po-Shan Huang)

指導教授 ： 李秀惠

共同指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.02394

摘要

微晶片技術的成長，讓超大型積體系統晶片設計不再是夢想。 隨著IP 數目的增加，各IP 之間的資料傳遞上成為了一大挑戰，為解決資料傳遞上所產生的問題，目前有許多研究提出以網格晶片(Network-on-Chip)的方式來解決IP 之間的資料傳輸問題。 網格晶片的研究著重於在晶片系統(System-on-Chip)中全域的資料傳輸。低傳輸延遲已經變成網格晶片和傳輸架構上最重要的課題。在晶片網路架構中，其主要元件為：路由器(Router)。在本篇論文中，我們提出一個運用在二維網路拓撲(2-D Mesh Topology)上之低傳輸延遲的行列交換器(Low-Latency RoCo Decoupled Router)，利用旁繞式輸出緩衝區達到高效能之目的。根據本篇論文實驗結果，當網路負載量到達30%，使用本篇所提之方法，平均可節省之延遲時間約6％。本篇研究可有效的提高路由器使用效率，來減少全域傳輸的網路壅塞。

關鍵字

網格晶片 ； 低傳輸延遲 ； 行列路由器 ； 輸出緩衝區 ； 網路壅塞

並列摘要

The scaling of microchip technologies has enabled large scale systems-on-chip(SoC). With ever increasing complexity of design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores.Network-on-chip (NoC) research addresses global communication in SoC. The low latency design is one of the most important issues to on-chip network design and the implementation of scalable communication structures. In the NoC, the main component is router. In this thesis, we propose a low-latency decomposed router used in the 2D mesh topology and, we can accomplish the goal of the high performance using detour output buffer (DOB). According to the experimental results, with the method mentioned in this thesis, the latency reduction can be achieved about 6% with light overhead on hardware and energy consumption. In this work, we can effectively increase the utilization of router to reduce the network congestion of the global communication.

並列關鍵字

Network-on-Chip ； Low Latency ； Row-Column Decoupled Router ； Output Buffer ； Network Congestion

參考文獻

[1] D. Bertozzi and L. Benini, “Xpipes: A Network-on-Chip Architecture for

pp.18-31, 2004.

[3] Benini, L., De Micheli and G, “Networks on chips: a new SoC paradigm” ,

IEEE Computer, Volume 35, Issue 1, pp.70 – 78, Jan. 2002

Exploration for Routers in a Hierarchical Network-on-Chip,” In Parallel and