隨著電子資訊產品體積小、效能高的設計趨勢,產品內部採用的晶片也逐漸朝向高腳數(I/O port)、高功率、體積小的方向演進,例如:微處理器、繪圖晶片、高速記憶卡…等。而覆晶封裝技術(Flip chip package)即能滿足此一類系統產品發展的需求,所以成為目前最受市場青睞的封裝技術之一,並且大量被用於個人電腦、行動電話及數位相機、MP3等高消費族群的領域。 覆晶封裝使用錫、鉛或金…等金屬材料製成凸塊,常見的如錫凸塊(Solder Bump)或金凸塊(Gold Bump)…等,用以取代傳統透過金線(Wire Bonding)連結的方式,使得整體I/O腳數的配置可以擴大為整個晶片(Chip)的表面,不再侷限於晶片的外圍,而其中”金凸塊級的覆晶封裝”(Gold Stud Bump Flip Chip, GSB_FC)技術又更加廣為被接受。 金凸塊封裝的覆晶方式主要有兩種:一為使用超音波覆晶的方式(Thermo-sonic Bonding)進行金對金的接合;另一則是使用熱壓覆晶的方式(Thermo-compression Bonding)進行金對錫的接合。目前在學術研究上,針對應用在金凸塊覆晶技術中的材料、金凸塊製程及應用的選擇已有不少的研究報告,但對於使用熱壓工法於金凸塊結合的研究報告尚屬少之,主要是因為影響覆晶熱壓接合的參數及變數甚多且又礙於專利的限制,故目前在台灣尚無封裝廠採用熱壓工法去製造並生產產品。 話雖如此,熱壓覆晶方式仍是一種適合大量生產且具低生產成本的封裝方法,故本研究將使用實驗設計法(Design of experiment)來找出影響熱壓覆晶製程的重要因子(Key Factor)及各因子間的交互作用並進行驗證,期望能夠將熱壓工法順利應用於金凸塊級的覆晶封裝中,而觀察的輸出則是以熱壓覆晶後的底膠孔洞面積(Voids)是否符合規格,來判斷此一覆晶參數是否適用及最終的電性測試(O/S test)結果為主。研究的測試工具為0.26mm厚度、尺寸14x14mm2的條狀基板(Strip substrate)並搭配0.15mm厚度、尺寸8x8mm2的晶片(Die);金凸塊材質的選用為4N (99.99%鋁)、1.0mils寬度的金線;底膠則選用非導電的膠材(Non-conductive paste, NCP)。 本研究的結果指出,晶片接觸基板的覆晶壓力、速度及接觸後各階段的覆晶結合溫度、時間…等因子都將對封裝後膠體孔洞(Voids)的面積有著相當重要的影響;另外覆晶結合的熱壓溫度與時間的控制,亦會顯著影響封裝後的電性測試結果。為確認此一最佳化參數的設定為適當的,本研究亦進行了驗證實驗,5個產品的驗證結果證實此一模型是正確且可接受的。
Over the years, flip chip has become the major interconnection method of high performance packages such as microprocessors, graphics chipsets, high speed memory and high-end ASICs. Flip chips apply in some high volume consumer product such as PC peripherals, mobile phones, digital cameras and MP3 players. Unlike conventional interconnection through wire bonding, flip chip uses solder or gold bumps instead. Therefore, the I/O pads can be distributed all over the surface of the chip, not only on the peripheral region. The "Gold Stud Bump Flip Chip" turns out to be the most popular flip chip technology among them. In the past two years, a key stimulus for this growth in gold stud bump flip chip applications has been the introduction a new generation of higher-speed, closer-pitch and high-density packages. And that it has the unique benefits and these benefits can be over the more common solder bump flip chips. One is reduced interconnection length and provides better conductivity and low resistivity. Another one is “Gold Stud Bump Flip Chips” offer finer spacing than most solder bumps, and it can be application to higher routing density, smaller and thinner packages. In this paper, the research is mainly with a view to develop a new process flow with low production cost for gold stud bump flip chip package. DOE (Design of experiment) methods are applied to analyze the experimental data to find the key factors of flip chip bond process. The result shows the thermo-compression flip chip bonding can be apply to gold stud bump flip chip package and the O/S test & NCP voids all can pass our spec.