使用離散式追蹤保持前置比較器之高速類比數位轉換器設計

本論文提出新型離散式取樣保持子電路，並且在這架構下能有效降低類比數位轉換器前端電路之每一級的負載電容值，用來改善類比數位轉換器的取樣頻率，在TSMC所提供的CMOS 1P6M 0.18µm製程中套用此離散式架構所設計出的規格為六位元，取樣頻率為1.6GS/s，而從訊號輸入所看進去的等效輸入電容為400fF，對系統應用來說，這會是個相當容易驅動的介面，另外在此篇論文中藉由使用時間緩衝的邏輯閘來改善一個摺疊解碼器，使之能夠套用在此轉換器上。模擬顯示此架構下的類比數位轉換器可以在輸入訊號為793.8MHz取樣頻率為1.6GS/s中，還可以擁有SNDR(Signal-to-noise and distortion ration)為35.81dB，換算成有效位元數則是5.66，在供應電壓為1.8V的全速運作底下，此類比數位轉換器消耗功率為310mW。

關鍵字

快閃式類比數位轉換器；溫度計碼至二進位摺疊碼編碼器；低輸入負載；離散式取樣保持電路

並列摘要

This work presents a new flash analog-to-digital converter (ADC) with distributed track-and-hold pre-comparators (THPCs). Utilizing the proposed architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 310mW from a 1.8-V supply at full operating speed.

並列關鍵字

Flash ADC ； Distributed ； Low input capacitence

參考文獻

[1] A. Batra, J. Balakrishnan, G.R. Aiello, J.R. Foerster, A. Dabak, “Design of a multiband OFDM system for realistic UWB channel environments”, IEEE Trans on Microwave Theory and Techniques, Vol.52, Sep. 2004, pp.2123~2138

[2] Quoc-Hoang Duong, T.-J.Park, E.-J. Kim, Sang-Gug Lee, “An all CMOS 743 MHz variable gain amplifier for UWB systems”, IEEE Symposium on Circuits and Systems (ISCAS), May 2006, pp.21~24

[4] B. Razavi, “Principles of Data Conversion System Design”, Wiley-IEEE Press, 1995, pp.7~11, 45~47, 96~101

[5] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design 2ed”, Oxford University Press, 2002, pp.652~656

[7] D.A. Johns, K. Martin, “Analog Integrated Circuit Design”, Wiley-IEEE Press, 1997, pp.448~452

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使用離散式追蹤保持前置比較器之高速類比數位轉換器設計

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