利用階層指配並考慮導熱矽穿孔
以最小化三維積體電路溫度上升

三維積體電路技術的發展使導線的長度能夠有效的縮減，因此能夠提高電路的速度與降低晶片的功耗。但是三維積體電路層與層之間的介質導熱率較低，當熱能通過堆疊的層之間時可能產生大量的熱能使晶片溫度升高。因此在三維積體電路的設計上，讓溫度的上升量降低是非常重要的。在高階合成階段，我們知道階層分配的結果對溫度上升的量有著顯著的影響。雖然之前的研究已經解決了階層分配與溫度上升之間的關係，但是他們並未考慮用於傳導垂直熱能的導熱矽穿孔之利用率，且值得注意的是導熱矽穿孔是一個降低三維積體電路溫度非常有效的技術方法。在本論文中，我們更進一步的對於溫度的上升同時考慮階層分配與導熱矽穿孔使溫度能更有效地降低。首先，我們研究了在高階合成階段的溫度模型，這包含了階層分配與導熱矽穿孔兩種模型。然後，我們提出了一個整數線性規劃方法以及一個啓發式演算法來正式制定減少溫度上升的問題。

關鍵字

直通矽晶穿孔；整數線性規劃；多層分割；熱導向；導熱矽晶穿孔；三維積體電路

並列摘要

Because of the reduction of wire length, the technology of three-dimensional integrated circuit can be used to improve the circuit speed and reduce the power dissipation. However, due to low thermal conductivities of dielectrics between active layers, the heat generated by the stacked layers may result in a large amount of temperature increase. As a result, in the design of 3D IC, it is very important to address the reduction of temperature increase. In the high-level design stage, it is recognized that the layer assignment result has a significant impact on the amount of temperature increase. Although previous works have addressed the relation between layer assignment and temperature increase, they do not consider the utilization of thermal through-silicon-vias (TSVs), which are vertical vias used only to convey heats. Note that the insertion of thermal TSVs is a very useful design technique to facilitate the heat transfer within 3D IC to reduce the temperature increase. In this thesis, we are motivated to perform simultaneous layer assignment and thermal TSV planning for further temperature increase reduction. First, we study the model of temperature increase (in the high-level design stage) that includes both the effect of layer assignment and the effects of thermal TSVs. Then, we propose an ILP approach and a heruristic algorithm to formally draw up our problem – to minimize the amount of temperature increase based on the model of temperature rise (in the high-level design stage).

並列關鍵字

Three Dimensional Integrated Circuits ； Multiple-Way Partition ； Thermal TSVs ； Integer Linear Programming ； Through Silicon Via ； Thermal Driven

參考文獻

[1] Arifur Rahman, Rafael Reif, “System-level performance evaluation of three-dimensional integrated circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 671-678, 2000.

[2] Rafael Reif et.al., “Fabrication Technologies for Three-Dimensional Integrated Circuits,” Proc. of IEEE International Symposium on Quality Electronic Design, pp. 33-37, 2002

[3] Yuh-Fang Tsai, Yuan Xie, N. Vijaykrishnan, Mary Jane Irwin, “Three-Dimensional Cache Design Exploration Using 3DCacti,” in Proceedings of the IEEE International Conference on Computer Design, 2005, pp. 519-524, 2005.

[4] D. L. Lewis, H-H.S. Lee, “A Scan-Island Based Design Enabling Pre-bond Testability in Die Stacked Microprocessors”, IEEE International Test Conference (ITC), pp. 1-8, 2007.

[7] M. Mukherjee and R. Vemuri, “Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems”, Proc. of ACM/IEEE International Conference on Computer Design, pp. 222—227, 2004.

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利用階層指配並考慮導熱矽穿孔以最小化三維積體電路溫度上升

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