應用於IEEE 802.11b 和WiMAX傳收器之分數型頻率合成器

Design of Fractional Frequency Synthesizer for IEEE802.11b and WiMAX Transceivers

陳世捷(Shi-Jie Chen)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

https://doi.org/10.6837/NCNU.2009.00036

摘要

無線通訊是近年來最熱門的研究議題，而其中引人注目的就是WiMAX（Worldwide Interoperability for Microwave Access，全球互通微波存取）。IEEE 802.16-2005（它之前的名稱是802.16e 或 Mobile WiMAX，這部分目前廣為使用）。
在本論文中，我們將會討論應用在IEEE 802.11b和WiMAX傳收器之分數型頻率合成器之研製。藉由新的除頻器單元電路採用TSPC架構的方法，可以大幅降低功率的消耗，並且採用了最小尺寸的MOS開關用來減少開關時產生的非理想效應，藉此獲得最小的晶片面積，並達到節省功率消耗的作用。
這個晶片採用國家晶片系統設計中心提供的TSMC 0.18μm Mixed-Signal 1P6M CMOS製程，完成分數型的頻率合成器晶片實作，包含了相位頻率偵測器、充電幫浦、迴路濾波器、電壓控制振盪器和除頻器，整體晶片面積為433μm × 346μm。晶片工作電壓為1.8V (VCO 1.2V)，輸入時脈速度為20MHz/11 MHz。除頻範圍為128-255。晶片整體消耗功率小於21.9mW。

關鍵字

分數型頻率合成器

並列摘要

In recent years, Wireless communication has become the most popular research topic, and the one of the most noticeable methods is WiMAX（Worldwide Interoperability for Microwave Access）. IEEE 802.16-2005（it used to be 802.16e or Mobile WiMAX，this part is most widely used in the recent years）.
In this thesis, we present a fractional synthesizer for 802.11b and WiMAX transceivers. The TSPC structure frequency divider cell we adopted here can substantially reduce the power consumption, and minimal size switch is used in the cell to avoid non-ideal effect of MOS switch and to achieve lower chip size and lower power consumption.
A fractional frequency synthesizer is implemented with TSMC 0.18μm Mixed-Signal 1P6M CMOS technology provided by Chip Implementation Center. Including the PFD,charge pump,low pass filter,VCO and programmable divider, the chip area is 433μm × 346μm. The chip works at 1.8V (VCO 1.2V) power supply and the input operates at 20MHz/11MHz clock rate. The divider modulus range is from 128 to 255 by fractional. The overall power consumption is less than 21.9mW.

並列關鍵字

Fractional Frequency Synthesizer

參考文獻

[1] Geum-Young Tak, Seok_Bong Yyun, Tae Young Kang, Byoung Gun Choi, and Seong Su Park, “A 6.3-9GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications,” IEEE Journal of Solid-State Circuits, Vol. 40, NO. 8, pp. 1671 - 1679, August 2005.

[2] June-Ming Hsu, Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang and Shen-Iuan Liu , “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 48,  Issue 9, pp.826 - 834,  Sept. 2001.

[3] Ching-Yuan Yang, Kuei-Zu Jiang and Jen-Wen Chen, “A Frequency Synthesizer Using Two Different Delay Feedbacks,” Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26, pp. 2799 - 2802 Vol. 3 May 2005.

[4] Chien-Hung Kuo and Yi-Shun Shi, “Positive Feedback CMOS Charge-Pump Circuits for PLL Applications,” MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, 2001. Volume 2, vol.2 14-17, pp.836 - 839, Aug. 2001.

[5] T. D. Loveless, L. W. Massengill, B. L. Bhuva, W. T. Holman, A. F. Witulski and Y. Boulghassoul, “A Hardened-by-Design Technique for RF Digital Phase-Locked Loops,” IEEE Transactions on Nuclear Science, Volume 53,  Issue 6,  Part 1, pp.3432 - 3438,  Dec. 2006.