應用於802.11a之低雜訊頻率合成器

Low-Noise Frequency Synthesizer for 802.11a

郭俊儀(Chun-Yi Kuo)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.00636

摘要

在各種無線通訊的標準仍普遍推行在2.4-GHz頻帶的80-MHz頻寬中工作之際，IEEE 802.11a無線通訊協定選擇在所謂國家資訊公用 (UNII) 的5-GHz頻帶來運行。這個頻帶能提供高速的資料傳輸，使得這個協定和在2.4-GHz頻帶的標準相比，能吸引更多無線傳統的鏈結以及行動通訊用這個協定來做實現。
然而，眾所週知的是，此系統的信號動態範圍 (dynamic range) 很大以及傳輸頻寬 (channel bandwidth) 很寬，若要將系統中的頻頻率合成器整合進射頻收發器的晶片之內，在頻率合成器的相位雜訊 (phase noise) 和其參考頻衍生雜訊 (reference spur) 之設計上都將面臨嚴峻的挑戰。在實現一個積體化的射頻頻率合成器時，鎖相迴路 (phase-locked loop) 通常被利用來克服因元件參數在製程或溫度上的變異而產生的壓控振盪器 (voltage-controlled oscillator, VCO) 在振盪頻率上的偏差。為了涵膏EEE 802.11a如此寬的工作頻帶，設計出來的壓控振盪器會具有一個相當大的增益 (KVCO)。雖然文獻上有發表釵h技術來避免此系統中的壓控振盪器具有太大的增益，它們仍無法在這麼高的頻率上同時達到工作頻帶寬以及低雜訊敏感度 (noise sensitivity) 的特色，尤其KVCO並沒辦法像在1.8-GHz系統中實現到20 MHz/V那麼小的值來降低整個頻率合成器的閉迴路雜訊敏感度 (closed-loop noise sensitivity)。
為了能同時在一個頻率合成器中達到上述兩個優點，我們提出了一個架構。這個架構由一個雙類比控制 (dual-analog-control) 的鎖相迴路以及一個數位頻率校正 (digital frequency-calibration) 電路組成。和傳統的頻率合成器相比，這個作品能提供一個很寬的工作頻帶以及適中的鎖定速度，且同時能在頻內相位雜訊 (in-band phase noise) 及參考頻衍生雜訊上表現出色。
在論文中，第二章會介紹鎖相迴路的基本理論以及頻率合成器的重要特性。之後會敘述如何設計一個頻率合成器的設計流程，並且用一些例子來做行為模擬 (behavioral simulation) 上的驗證。
第三章一開始先描述這個作品的設計要點。對於這個頻率合成器，頻譜的表現、可工作頻帶，以及鎖定速度的考量都是相當關鍵的。接著，此論文中提出的架構將被詳細地分析探討。
整個頻率合成器的設計與實現將在第四章中詳述，此作品是在一個0.18微米互補式金氧半導體混合信號製程 (CMOS 0.18-μm 1P6M mixed-signal technology) 中作實現。
最後，在第五章中，我們對這個論文作個結論，其中包含這個作品的效能列表及其與文獻上的作品的比較；論文中重要的觀點會再次提及，而值得在這個架構上繼續深入探討的項目也會加以敘述。
附錄A收錄了一個和此應用相關的作品 – 一個寬頻的5.8-/5.2-/2.4-GHz矽鍺LC壓控振盪器，它實現在一個0.35微米矽鍺雙極互補式金氧半導體 (BiCMOS) 的製程中。這個壓控振盪器採用一個混合式的頻率調整機制：運用電感性配合電容性的切換實現而成的頻率調整機制，能讓這個壓控振盪器能具有多頻帶 (multiband) 的振盪特性也能在振盪頻帶中具有很寬的可調頻率範圍 (tuning range)。

關鍵字

鎖相迴路 ； 頻率合成器 ； 無線區域網路

並列摘要

As various wireless standards continue to populate the 80-MHz spectrum in the 2.4-GHz band, the IEEE 802.11a operating in the 5-GHz unlicensed national information infrastructure (UNII) band which allows high-speed data communications become more attractive and fascinates more realization of wireless link and mobile communication, compared to the 2.4-GHz counterpart.
It has been well acknowledged that integration of an RF frequency synthesizer into a transceiver poses great challenge because the large dynamic range of the input signal and wide channel bandwidths have set stringent requirements for the synthesizer phase noise and spurious sideband levels. To implement an integrated RF frequency synthesizer, phase-locked loops are usually utilized to cope with variations in the device parameters with process and temperature resulting in frequency variations of the voltage-controlled oscillator (VCO). Such implemented VCO nevertheless translates to a quite large gain (KVCO) for the coverage of the wide operating range of IEEE 802.11a. While techniques to avoid large KVCO have been developed, the characteristics of wide-range and low-sensitivity still may not be realized concurrently in that high frequency of 5 GHz. In particular, the KVCO is difficult to design as small as around 20 MHz/V to reduce noise sensitivity of the closed-loop, as is in contrast feasible in 1.8-GHz applications.
To achieve both the two goals within a single frequency synthesizer, a topology composed of a dual-analog-control PLL and a digital frequency-calibration circuit is proposed. Compared with traditional frequency synthesizers, this work exhibits a wide operating range and a reasonable settling speed while performing well on in-band phase noise and reference spurs.
Chapter 2 will give basic ideas of phase-locked loops (PLLs) as well as some important characteristics in a frequency synthesizer. A design flow is described along with detailed parameter setting and Architecture simulations together with some examples are demonstrated.
In chapter 3, the design considerations of this thesis will be introduced. Concerns including spectral purity, operating range, and switching time are all crucial. Detailed analysis of the proposed architecture will be presented thereafter.
Chapter 4 contains the design and implementation of the proposed synthesizer in a CMOS 0.18-μm 1P6M mixed-signal technology.
Chapter 5 will give a conclusion to this work, providing a performance summary and comparison with those works in the literature. Key results together with issues that should be noted for future perspectives are reinforced and summarized.
Appendix A presents a related work – a 5.8-/5.2-/2.4-GHz SiGe LC VCO with wide tuning range. Implemented in a 0.35-μm SiGe BiCMOS technology, this VCO utilizes a hybrid frequency-selecting scheme: by inductive band- switching and capacitive frequency-tuning, this VCO achieves both multi-band and wide range characteristics with a control voltage from 0- ~ 3.3-V.

並列關鍵字

phase-locked loop ； PLL ； wireless local area network ； WLAN ； frequency synthesizer

參考文獻

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[4] H. R. Rategh, H. Samavati, and T. H. Lee, “ A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE Journal of Solid-State Circuits, vol.35, pp. 780~787, May 2000.

[5] C.M. Hung and K. K. O, “ A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop,” IEEE Journal of Solid-State Circuits, vol.37, pp. 521~525, Apr. 2002.