以0.18微米CMOS技術設計及實現之W頻帶巴倫單端至差動轉換器

Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology

劉峯誠(FENG-CHENG LIU)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/光電科技碩士學位學程/碩士(2014年)

https://doi.org/10.6837/NCNU.2014.00059

摘要

我們利用台積電0.18 μ m CMOS製程技術來實現 CMOS RFICs 射頻前端被動元件W頻帶巴倫之設計與量測。採用Marchand balun平衡-非平衡轉換器、進而架構搭配輸出匹配網路，利用晶片設計之多層式結構增加耦合量達到電路所需之相位差。
量測結果需在振幅不平衡需小於 ±1.5 dB，相位不平衡需小於 ±10°所有傳輸走線均使用Sonnet 模擬，由Agilent ADS 進行共同模擬，務必要求佈局與模擬一致。量測頻率為77~81GHz，並將總晶片面積控制為0.55 mm2 之內。
模擬結果符合設計需求，透過晶片設計製作中心(Chip Implementation Center)實現馬遜巴倫，緊接著透過國家奈米元件實驗室(National Nano Device Laboratories)執行量測110GHz元件高頻S參數量測系統，量測結果與設計模擬進行設計與實現之實務操作。

關鍵字

W頻帶 ； 馬遜巴倫 ； 平衡-非平衡轉換器

並列摘要

We use TSMC 0.18 μ m CMOS process technology to achieve CMOS RFICs W-band RF front-end design and passive component measurement Barron's. Marchand balun using balanced - unbalanced converter, thereby architecture with output matching networks, to increase the coupling circuit to achieve the required amount of phase difference between the use of multi-layered structure of the chip design.
Measurement results need not be in amplitude balance must be less than ± 1.5 dB, phase imbalance must be less than ± 10 ° all transmission traces were simulated using Sonnet, conducted jointly by the Agilent ADS simulation, be sure to be consistent with the requirements layout simulation. Measurement frequency is 77 ~ 81GHz, and the total chip area of 0.55 mm2 control within.
The simulation results meet the design requirements and achieve Marchand balun through Chip Implementation Center (CIC), followed by to perform high-frequency measurements 110GHz element S-parameter measurement system through the National Nano Device Laboratories(NDL), measurements performed with the design simulation design and implementation of practical operation.

並列關鍵字

W-Band ； Marchand Balun ； balance to unbalance transformer

參考文獻

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