考量多核心三維堆疊記憶體架構晶片使用情形之溫度與效能分析

Scenario-Aware Thermal Analysis in MPSoCs with 3D-Stacked Memories

陳虹熹(Hung-Hsi Chen)

指導教授 ： 陳依蓉

國立暨南國際大學/科技學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6837/NCNU.2013.00078

摘要

三維堆疊技術將多核心處理器與記憶體元件，以堆疊方式整合於同一晶片以降低之間傳輸時間，並利用低傳輸時間與高密度之穿矽通孔連接處理器與記憶體，以提供大量記憶體頻寬。然而，三維堆疊技術會使晶片功率密度提高，導致系統升溫度速度提高。因此，為使系統能夠在不超過溫度限制下達最佳效能，其中一個方法為根據系統之特性設計堆疊記憶體架構。常見之記憶體元件有動態與靜態存取記憶體兩種，且其存取耗電、單位面積可存放之位元數，與存取速度等，各有不同。因此，系統中應該選用多少層數之動態或靜態記憶體晶片，應就系統的執行特性，與對溫度的影響，來選擇合適的記憶體元件配置。在本篇論文中，我們分析多核心系統晶片(MPSoC, Multi-Processor System-on-Chip)，在不同堆疊記憶體架構下，其記憶體系統效能表現，與系統最高溫度之間的關係。在系統行為分析方面，我們考量到大部份系統晶片會在某執行情境下(scenario)，執行一組特定的程式，而系統行為通常可用多組不同執行情境來表示之。因此我們在本論文中，著重於分析不同執行情境的行為，如何去影響對記憶體系統效能以及熱的行為。另外我們透過觀察分析，找出不同執行情境的時候，在溫度不要過高的前提下，找到能讓效能盡量提高的適合的記憶體堆疊方式。我們的分析發現，需要的記憶體大小較小時，可以利用靜態存取記憶體的快速存取的優點來當作上層記憶體元件；而當需要的記憶體大小較大時，則利用動態存取記憶體功耗較低的優點來當作上層記憶體元件；此外由於路由器的存取時間比處理核心以及記憶體還長，所以必須注意資料配置的方式，以避免需要透過路由器傳送資料而造成執行時間過長的現象。我們的分析結果，為設計使用三維堆疊技術整合記憶體之多核心系統晶片之重要依據。

關鍵字

三維晶片堆疊 ； 多核心處理器系統晶片 ； 特定應用程序 ； 執行情境

並列摘要

The 3D integration technology utilizes the low-latency and high density TSVs (Through Silicon Vias) to integrate memories and cores in the third dimension. Although the 3D integration technology provides abundant memory bandwidth, the power density also increases with the number of chip stacks. For system designs, DRAMs and SRAMs are two commonly utilized memory modules, and the two memory modules have very distinct performances in access latency, access power, and memory storage density. Therefore, to maximize system performance while the thermal constraint is met, the design of the memory chip stack of the system should be carefully designed accoding to the needs of the target system. To perform a proper design of the stacked memory architecture, we first have to characterize how different memory chip stack designs perform with the target workload in terms of performance and thermal behavior. Since the executions of embedded systems can be described by a set of scenarios, where each scenario indicates a specific set of applications, we perform scenario-aware thermal analysis for MPSoCs (Multi-Processor System-on-Chips) with 3D-stacked memories. Our experimental results show that　when the required memory size is small, we can use the SRAM advantages of quick access as the upper memory components. Otherwise, when the required memory size is large, we use DRAM as upper memory element. In addition, because the access time of router is longer than the processing cores and memory, so we must pay attention to the way of data allocation, to avoid the need to send data through the router. Our characterization results provide guidelines for embedded system designers when performing 3D-stacked memory system design.

並列關鍵字

3D die-stacked ； MPSoC ； application-specific ； scenario

參考文獻

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