考慮溫度相依之多核心系統晶片測試排程

Temperature-Dependent Test Scheduling for Core-Based System-on-Chip Design

邱景群(Ching-Chun Chiu)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

https://doi.org/10.6840/cycu201500701

摘要

在系統晶片上，溫度對測試的影響越來越受到關注，特別是對於不同的測試應該在不同的溫度範圍內執行。測試經由TAM Bus連接至外部測試機台(ATE)，但是TAM Bus同一時間能執行的核心有限，因為受到位元(width)的限制，所以如何適當的分配TAM Bus位元對於測試排程的總時間長度有很大的影響，然而之前對於溫度相依的測試研究文獻較忽略TAM Bus位元分配的重要性。
基於上述觀察，我們提出一個兩階段式演算法，第一階段為TAM Bus位元分配，第二階段為溫度相依的測試排程。經由兩階段式的演算法可以達到位元的最佳利用，避免空乏時間的浪費，並且考慮測試溫度，利用升溫排程及降溫排程，讓所有的測試都在指定的溫度範圍內執行。經由結合TAM Bus位元分配及溫度相依的測試排程，可以達到最小化總測試時間長度並提高測試效率降低成本的目標。

關鍵字

測試排程 ； 溫度相依缺陷 ； TAM Bus位元分配

並列摘要

Recent research has shown that temperature-dependent testing, which applies different tests at different temperature ranges, is needed for system-on-chip (SoC) designs. However, previous temperature-dependent testing algorithms assume that two external tests cannot utilize the test-access mechanism (TAM) at the same time. In fact, if the external tests of different cores do not use the same TAM bus wire, they can be executed concurrently for reducing the test application time. Based on this observation, in this paper, we propose an effective and efficient algorithm to perform the simultaneous application of test scheduling and TAM bus wire assignment for temperature-dependent SoC testing. Compared with previous algorithms, experimental results consistently show that the proposed approach can greatly reduce the total test application time.

並列關鍵字

Test Scheduling ； Temperature-Dependent defect ； TAM Bus Assignment

參考文獻

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