應用於生醫之軌對軌輸入低電壓低功率十位元 連續趨近式類比至數位轉換器

Rail-to-Rail Input Low Voltage Low Power 10-bit Successive Approximation ADC for Biomedical Applications

薛啟遠(Chi-Yuan Sueh)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2011年)

https://doi.org/10.6837/NCNU.2011.00120

摘要

本論文提出一個應用於生醫之軌對軌輸入低電壓低功率十位元連續趨近式類比至數位轉換器。此轉換器包含比較器、追蹤與保持電路、數位至類比轉換器、連續趨近式暫存器、暫存閂鎖器和重置電路。考慮到精準度的要求，使用二位元權重的電容陣列，且為了降低功率消耗，運用三明治電容結構來完成小電容。考量雜訊與功率消耗，使用單位電容值約為4.88fF，使整體電容值約為5pF，除此之外，在低電壓操作和低電壓輸入下，吾人使用Vdac逼近參考電壓來完成軌對軌輸入。

本論文之晶片使用國家晶片系統中心所提供的TSMC 0.18μm 1P6M CMOS製程來設計與實現，晶片之核心面積為231μm×276μm (0.0638mm2)，整體晶片包含PAD面積為680μm×780μm (0.5304mm2)。工作電壓操作在0.9V，工作頻率為2.4MHz，取樣率為200kS/s，輸入頻率在1.565kHz時，SNDR為60.837dB、功率消耗為2.3415μW、FOM為13.02fJ/conversion、ERBW可達Nyquist rate。

關鍵字

連續趨近式 ； 類比數位轉換器 ； 低功率 ； 軌對軌輸入

並列摘要

A low voltage and low power 10-bit SAR ADC for biomedical applications is proposed in this thesis. The SAR ADC is composed of a comparator, track and hold circuit (T/H), digital to analog converter (DAC), successive approximation register (SAR) and latch, and reset sub-circuit. Binary-weighted capacitor array is used for taking into account the requirements of accuracy. Sandwich capacitor structure is employed in order to accomplish small size capacitors as well as to reduce power consumption. Considering the noise and power consumption, a unit capacitance value of approximately 4.88fF is used, therefore, for reducing the total capacitance value of DAC to be 5pF. In addition, for the low supply and input voltage operation, we use the scheme of Vdac approaching Vref to achieve the rail to rail input operation.

The chip designed in this work is using TSMC 0.18μm CMOS process provided by Chip Implementation Center (CIC). The core area of the chip is 231μm×276μm (0.0638mm2), and the total area including pads is 680μm×780μm (0.5304mm2). The simulation results show that the signal-to-noise-distortion ratio of the ADC is 60.837dB at 200kS/s sampling rate and 1.565kHz input frequency with power consumption of 2.3415μW from a 0.9V supply voltage and an ERBW up to its Nyquist bandwidth. The figure of merit is 13.02fJ per conversion step.

並列關鍵字

SAR ； ADC ； Low power ； Rail to rail input

參考文獻

[1] Pascal Meinerzhagen, “Design of a 12-bit low-power SAR A/D Converter for a Neurochip,” Master’s Thesis, Microelectronic Systems Laboratory, Swiss Federal

Institute of Technology, Lausanne (EPFL), Switzerland and University of California, Merced, California, USA, 2008

[2] 高碩廷, 一個0.8-V低功率類比前端積體電路應用於生醫訊號紀錄,國立交通大學電機與控制工程研究所碩士論文,2008.

[3] Yung-Jui Chen, Kea-Tiong Tang, Wai-Chi Fang, “An 8μW 100kS/s Successive Approximation ADC for Biomedical Applications,” IEEE/NIH Life Science Systems and Applications Workshop, (LISSA) 2009, Betheda, USA.

[4] Wen-Yi Pang, et al., “A 10-bit 500-kS/s low power SAR ADC with Splitting comparator for bio-medical applications,” IEEE Asian Solid-State Circuits Conference, 2009, pp. 149-152.