低成本薄膜電晶體液晶顯示器源極驅動器之研究

本論文第一個電路提出一種六位元源極驅動器(source driver)，此架構是使用一組非線性電組串(nonlinear R-string)給多組數位類比轉換器(DAC)使用，每一組DAC產生電壓至channel輸出，並利用有限個數的緩衝器(buffer)穩定迦瑪電壓(gamma voltage)。本論文提出的電路有效減少buffer個數並穩定電組串上的電壓，進而達到降低成本的優點。本論文第二個電路提出一個新的源極驅動器架構以降低薄膜液晶顯示器(TFT LCD)晶片佈局面積，達到低成本的目的。DAC在源極驅動器中佔了極大的面積。因此本專題利用一個DAC decoder提供給兩個channel使用，使DAC的decoder數目減少一半，晶片面積即可減小以降低成本。本專題也有做charge recycle來減少功率消耗。

關鍵字

源極驅動器；液晶顯示器；非線性電組串；數位類比轉換器；迦瑪電壓

並列摘要

In the first part of the thesis, A 6-bit source driver circuit has been proposed. The architecture utilizes a set of nonlinear resister string to provide the reference voltages to all of the R-DACs (digital-to-analog converters). Each R-DAC is responsible for one LCD (liquid crystal display) channel. A few of gamma buffers are used to make the gamma voltages stable. In the new architecture, the number of buffers can be greatly reduced by using less gamma buffers in front of the resister string instead of buffering each output voltage of the channel with one output buffer. Hence, the low cost and low power consumption source driver can be realized. The second circuit in this thesis is suitable for the large panels. A new architecture of the source driver is presented to reduce the chip area. The DACs occupy the most part of the chip areas in the source driver. In our new architecture, one DAC decoder can be used in the two channels by the way of the elaborate arrangement. Then, the number of DAC decoder can be reduced by half, and chip can be save area close to a half. Besides, the charge recycling method is also be added in this circuit to reduce power consumption.