暫存器陣列式快速傅立葉轉換處理器之超大型積體電
路設計

論文名稱：暫存器陣列式快速傅立葉轉換處理器之超大型積體電路設計校院系：國立暨南國際大學科技學院電機工程學系研究所頁數：66 畢業時間：2007/07 學位別：碩士研究生：張銘哲指導教授：吳俊德博士論文摘要本篇論文提出一顆具有快速傅立葉轉換處理器的晶片，專門應用於語音信號辨識之使用。這個系統主要包含個主要的部份，分別是快速傅立葉轉換(fast Fourier transform)處理器、梅爾倒頻譜參數(Mel-scale frequency cepstral coefficient)擷取晶片以及算數邏輯運算單元(ALU)架構的數位信號處理器。其中數位信號處理器和梅爾倒頻譜參數擷取晶片已經被之前的學長所實現，在這篇論文我們採用一種新的暫存器陣列方法並使用radix-22 管線式的架構來設計，為了降低晶片的功率消耗以及計算量。最後此晶片應用TSMC 0.18um 標準單元(standard cell)合成出處理器電路， FFT/IFFT 處理器Gate count 約為196172，而latency 時間約為2.56μs，工作頻率為 100MHz。

關鍵字

快速傅立葉轉換；數位信號處理器；語音信號辨識

並列摘要

Title of Thesis: VLSI Design of Register Array Based Fast Fourier Transform Processor Name of Institute: Depar tment of Elect r ical Engineer ing Col lege of Science and Technology Nat ional Chi Nan Univer si ty Pages: 66 Graduation Time: 2007/07 Degree Conferred: Master Student Name: Ming-Che Chang Advisor Name: Dr. Gin-Der Wu ABSTRACT This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a register array based fast Fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. The DSP processor and MFCC processor had been implemented by previous researcher. In this FFT processor, we proposed a novel register array based pipelined radix-22 structure to reduce power consumption and computation cycles. The chips are synthesized by TSMC 0.18um cell library. The gate count of the FFT chip is about 196172. The latency is about 2.56μs. The FFT chip is work at 100 MHz.