高解析度雙波段紅外線影像讀取介面設計與實現

Design and Implementation of High Resolution Readout Interface with Dual-Band Infrared Image

王騰翊(Teng-Yi Wang)

指導教授 ： 孫台平

國立暨南國際大學/科技學院/光電科技碩士學位學程/碩士(2013年)

https://doi.org/10.6837/NCNU.2013.00260

摘要

訊號介面電路於紅外線陣列感測系統中重要性僅次於讀取電路，它扮演著類比訊號與數位訊號間之溝通橋樑，因此本論文將探討訊號介面電路並將其設計與實現，先將其整合於單波段感測讀取電路之系統驗證，再搭配先導型雙波段感測架構來驗證，將系統整合為可單輸出與雙輸出切換之架構。藉由此小陣列讀取系統驗證之結果，再將其理論擴展至320x256大陣列讀取系統，如次即可得知訊號介面電路於當下系統介面適用與否，亦可將設計理念與介面電路設計想法延伸至640x512等更大陣列讀取系統來判斷適用性。
紅外線影像介面系統設計主要包含緩衝放大器、低通濾波器、高速類比數位轉換器與FPGA(Field-programmable gate array)，將其整合開發成讀取電路訊號介面模組板。此系統利用FPGA提供數位控制訊號，主要供給陣列讀取電路與類比數位轉換器時脈，系統訊號方能同步處理、輸出、儲存與顯像。當前端陣列讀取電路將感測器訊號轉換為電的訊號，再經由訊號介面板處理後傳送至FPGA開發板，藉由FPGA對訊號處理與運算再傳送至開發板中顯像電路後於螢幕上顯像。
紅外線陣列感測系統之訊號介面電路板於先導型讀取晶片中驗證，陣列大小分別為10x8及16x12兩種，訊號介面電路經穩定度驗證後解析度可達11 bit，系統整合後系統解析度亦可達到9 bit，符合開發板之顯像輸出解析度。系統像素輸出速度極限為1.47MHz，濾波器採用unit gain Butterworth二階低通濾波器之架構設計，高速類比數位轉換器為12 bit 逐漸逼近式架構，整體系統各像素轉換時間約681ns，理論訊號延遲時間約340ns。

關鍵字

讀出電路 ； 濾波器 ； 訊號介面板 ； FPGA ； 陣列顯示

並列摘要

In the sensory system with infrared array proxy board is important only next to readout interface circuit. It acts as a bridge to like between the analog signal and the digital signal. The thesis explores how to design and implement the proxy board. The first step is to integrate with the single-band ROIC to validate the readout system. Secondly, integrate with the pilot dual-band ROIC to validate it. Third, integrated switch mode with single output and dual output. By the results of this verification it could be deployed into 320x256 larger size of array readout system and also be verified the suitability of proxy board. With skillful technology design concept and proxy board design ideas it could further expand into a 640x512arrays readout system and verify the suitability of proxy board too.
Developing as an integrated readout interface circuit model board the Infrared imaging proxy board design includes buffer amplifier, low-pass filter, high-speed analog to digital converter and FPGA (Field-programmable gate array). The system of thesis using FPGA provides digital control signal to ROIC controller, ADC clock cycle and display. It could be sync signal with processing, output, storage and display at the same time. Array readout circuit converts sensor signals to electrical signals, and then transmits to FPGA development board via the proxy board. Signal transmits to the video interface board and display after FPGA processing.
The system of proxy board is validated on pilot-readout chips with array size of 10x8 and 16x12. The proxy board resolution could get as fine as 11 bit on stability verification. Even integrated as a system the least resolution of 9 bit is easily matched on the development of the system board which meets the video display output resolution. Pixel output rate is operated at 1.47MHz, while the second order unit gain Butterworth low-pass filter is adopted in filter design architecture, and the architecture of analog to digital converter is 12 bit gradually approached. Therefore the overall system conversion time for each pixel is 681ns and the signal delay time is 340ns.

並列關鍵字

Readout Integrated Circuit ； Filter ； Proxy Board ； FPGA ； Image Display

參考文獻

[1] Jian-Cheng Ye “Advance Integrated Readout Circuit Design for Single and Dual Band Infrared Focal Plane Array” National Chi Nan University Department of Electrical Engineering Master Thesis, 2010.

[2] I-Tin Liu “Research of Capacitor Transimpedance Amplifier for Infrared Readout Integrated Circuit Design” National Chi Nan University Department of Electrical Engineering Master Thesis, 2011.

[3] Tzeshin Chen “The Research of Capacitive Trans-Impedance Amplifier and Direct Injection Readout Integrated Circuit Design for the Photo Focal Plane Array Detectors and Wireless Transmission Applications” National Chi Nan University Department of Electrical Engineering Master Thesis, 2011.

[4] Hung-Yu Chen “Hardware Implementation of Real-time Moving Object Detection with FPGA” Fu Jen Catholic University Department of Electronic Engineering Master Thesis, 2008.

[5] 鄭光欽 Verilog硬體描述語言實務, 初版, 全華圖書, 新北市, 2011.