隨著科技的發展,DDR模組廣泛地應用遍及電腦、資訊、通訊和消費性電子…等領域,扮演著資料記憶存取的重要功能。當電子產品的運作速度不斷提高,就得需要速度更快的記憶體來處理這些傳輸的資料,這使得系統裡CPU與記憶體之間的佈線設計越來越難處理。因此,如何在電路板上滿足越來越嚴苛的佈局要求將成為一個重要的課題。 本研究著重於FPGA與DDR3上的匯流排佈局,搭配Cadence Allegro的SI進行佈局前/後的模擬與分析。並以眼圖(EYE Diagram)作為波形分析的依據。藉由各種佈線的方式彙整出有用的記憶體匯流排佈局準則,藉此達到高速電路板上信號完整性與嚴苛時序的要求。
With the development of technology, DDR modules, with their important functions for accessing data memory, have been widely applied in the fields of computer, information, communication, consumer electronics, etc. When the processing speed of electronic products continues to improve, the need of haveing faster memory to process transmitted data makes the routing design between CPU and memory more difficult to be handled. Therefore, how to meet the increasingly demanding requirements of layout on circuit boards has become an important issue. This study focuses on the bus layout of FPGA and DDR3. Adopting Cadence Allegro SI for the simulation and analysis of pre- and post-layout, the eye diagram is also used as the basis of waveform analysis. By looking into the various ways of routing, this study aims to compile a guideline for memory bus layouts and meet the demands of signal integrity and stringent clock requirements on high-speed circuit board.