FPGA與DDR3 SDRAM資料匯流排佈局設計

FPGA and DDR3 SDRAM Data Bus Layout Design

吳建霆(Chien-Ting Wu)

指導教授 ： 張茂林

健行科技大學/電資學院/電機工程所/碩士(2012年)

https://doi.org/10.6824/UCH.2012.00045

摘要

由於資訊電子產品不斷地提高運作時脈以增進性能。這使得系統裡CPU與記憶體之間的連線設計越來越難處理。為提高效能，DDR3除了有更快的位元傳輸率（從400Mbps起跳，最高達1.6Gbps）外，也在連線拓樸上有很大的改革（從T-topology變為Fly-by topology）。因此，如何在電路板佈局上滿足越來越嚴苛的要求變成一個重要的課題。
隨著數位系統中工作時脈頻率迅速提高和信號上升（下降）時間不斷變短，PCB線路連線和電路板層級特性對系統電氣性能的影響也越來越重要。對於低頻設計，線路連線和電路板層級影響可以不考慮；但當頻率超過50MHz時，連線關係和電路板層級特性的影響不容忽視，必須對傳輸線效應加以考慮。因此，高速系統設計必須面對連線的傳輸線效應引起的信號完整性及時序等問題。
在記憶體部分，目前比較普遍使用中的DDR2速度已經高達800Mbps，而DDR3速度甚至高達1600Mbps。對於如此高的速度，從PCB的設計角度來講，要做到嚴格的時序要求，以滿足信號的完整性，已成重大的挑戰。記憶體為了滿足越來越高的資料傳輸率，其硬體架構也越來越複雜。

關鍵字

記憶體 ； 雙倍資料率 ； 匯流排 ； 佈局

並列摘要

Information and electronic products continue to improve the operation of the clock in order to enhance performance. This makes the design of the connection between the CPU and memory in the system more and more intractable. To improve performance, DDR3 addition to the faster bit rate (from 400Mbps up to 1.6 Gbps), the highest is also a lot of reform on the connection topology (from the T- topology into a Fly-by topology). Therefore, how to meet the increasingly stringent requirements to become an important issue in the circuit board layout.
With the rapid increase in clock frequency in the digital system and signal rise (fall) time is constantly shorter PCB lines connection and board-level features of the system electrical performance is increasingly important. For low-frequency design, the line connection and the board level can be taken into account; but when the frequency exceeds 50MHz, the connection relations and board-level characteristics can not be ignored, transmission line effects must be taken into account. Therefore, the high-speed system design must face signal integrity and timing problems caused by the connection of transmission line effects.
In the part of the memory, the more common use of DDR2 rate up to 800Mbps, and even up to 1600Mbps DDR3 rate. For such a high speed PCB design, to achieve the strict timing requirements, in order to meet signal integrity has become a major challenge. In order to meet the increasingly high data rates, the hardware architecture of memory is more complex.

並列關鍵字

Memory ； Double Data Rate ； Bus ； Layout

參考文獻

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