以暫存記憶體整合高階合成編譯器支援的FPGA硬體架構

A Scratchpad Memory for High-Level Synthesis Compiler on FPGA

蔡偉哲(Wei-Che Tsai)

指導教授 ： 王勝德

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.00789

摘要

高階合成的編譯器通常可以生成幾種不同的硬體讓使用者選用，然而編譯器預設的硬體架構不可能適應所有使用者的需求。我們提出了一個使用者易於客制化的硬體架構，其中的編譯器是修改自LegUp高階合成編譯器且加上暫存記憶體來加速編譯器所產生的硬體，此外我們使用雙埠記憶體來增強效能。暫存記憶體內容的選擇則是由一個基於線性規劃的演算法來決定，此演算法在編譯時分析源始碼以求得一個最佳化的記憶體配置。實驗的結果展示使用暫存記憶體後，程式執行的時間只需原本只用SDRAM時的23%~43%，而且使用SDRAM加上暫存記憶體可以解決比較大的問題。

關鍵字

高階合成 ； 編譯器 ； 暫存記憶體 ； FPGA

並列摘要

High-level synthesis (HLS) compilers usually provide some supported target architectures that can be chosen by users; however, the limited architectures may not fit the requirements of underlying systems. In this paper, we propose a target architecture embedded with a scratchpad memory (SPM) and an SDRAM that allows users to customize their design. The proposed architecture has been integrated with an HLS compiler, called LegUp, so that the synthesizing computation can be executed on the target architecture with the SPM and the SDRAM. In addition, we use a dual port memory controller to enhance the performance of the target architecture. An algorithm based on integer linear programming is used to allocate data to the proposed SPM at compile time. The experiment results show that the proposed architecture can effectively achieve the 23%~43% execution time of an architecture without an SPM, and can solve huge problems by using the external memory.

並列關鍵字

High-level Synthesis ； Compiler ； Scratchpad Memory ； FPGA

參考文獻

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