用於資料密集型運算之高擴展性FPGA硬體加速平台

High Scalability FPGA-based hardware accelerator for data-intensive computation.

李岱樺(Dai-Hua Li)

指導教授 ： 鍾菁哲

國立中正大學/工學院/資訊工程學系/碩士(2015年)

摘要

隨著物聯網興起，不論是智慧型手機、社群平台或感測裝置，所有設備都希望能夠經由網路跟伺服器交換資料，讓使用者能夠即時得到回覆，也因此面臨大數據 (Big data) 的時代，海量的資料、不同的資料型態、隨時隨地的資料傳遞，隱藏在資料裡的價值，都是處理大數據會面對的問題。
分散式系統和雲端計算也越來越普遍，希望藉由多個運算伺服器或叢集做平行化的運算，和互相使用存取空間讓容量上升，來彌補個人電腦儲存的空間不足和CPU運算速度的瓶頸。也因為個人電腦上的瓶頸，越來越多人使用硬體加速平台(hardware accelerator)來分擔運算的負擔，最常見的就是可程式邏輯陣列(FPGA)和圖形處理加速器(GPU)。硬體加速平台適合做高密度且獨立的運算，它具有很多運算單元可以達到運算平行化。
K-means分群演算法是資料探勘(data mining)的一種，可以用來分析資料間的關聯性或是圖片的優化，而本論文也實現K-means分群演算法分析大型的資料，呈現出硬體加速平台的優勢。因此，我們建立了一個以FPGA為基礎的擴充平台，利用網路分享器來提升擴充性(scalability)。電腦端把資料整理好傳給FPGA，經由FPGA計算完後，再把結果傳回給電腦端。電腦端負責較不規則的運算處理，工作分配和處理FPGA的運算結果，而FPGA只要專注於運算的部分。最後再以執行時間來評斷系統的表現。

關鍵字

K-means 分群演算法 ； 以FPGA為基礎的擴充平台 ； 大數據 ； 現場可程式邏輯門陣列硬體加速平台

並列摘要

Nowadays, the smart phones, web systems, and wireless sensors are enabled to connect the Internet, and response to user in real time. Therefore, we are living in the internet of things (IoT) era with big data generation. The “4Vs” characteristics of big data such as variety, volume, velocity, and value make them difficultly to be handled.
The personal computer is hard to deal with big data, because the capacity of memories and storage devices is not enough and the limited processing rate of the CPU. Therefore, the distributed file system and cloud computing have become popular. Both of them can compute in parallel and share the data of disks. Moreover, the hardware accelerator is suited for data-intensive computation, and the function units of hardware accelerator are processed in parallel. Graphic processing units (GPUs) and field programmable gate arrays (FPGAs) are potential hardware accelerators.
K-means clustering algorithm is one of the data mining techniques. K-means is used to find the relation between the data, or for image processing. Therefore, in this thesis we implement k-means clustering algorithm to analyze the dataset. The FPGA-based hardware accelerators that communicate with computer through switch are proposed. The computer wraps data into packets to FPGA, and it receives data after the FPGAs are finished computation. In addition, the host computer is employed as the master to manage data and dispatch jobs, and the FPGAs are focused on accelerating data computation. Finally, the proposed system performance is compared with the benchmark execution time.

並列關鍵字

FPGA-based hardware accelerators ； K-means clustering algorithm ； field programmable gate ； big data

參考文獻

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