FPGA加速硬體模擬

FPGA Accelerated Hardware Co-simulation

何翊模(Yi-Mo Ho)

指導教授 ： 洪士灝

國立臺灣大學/電機資訊學院/資訊網路與多媒體研究所/碩士(2018年)

https://doi.org/10.6342/NTU201800567

摘要

在硬體開發期間,如何讓軟體開發者可以在虛擬平台上快速與精確地程式分析,是當前很重要的研究議題。而FPGA有著能源節省、適合大量整數運算以及能夠反覆重組以適應不同的工作需求的好處,如此的結構同時擁有硬體的速度以及軟體的彈性,近年逐漸受到廣泛使用。本論文中,我們希望透過FPGA來加速我們實驗室的效能分析工具(VPMU)快取部分的模擬來讓使用者可以更快地對程式進行分析。

關鍵字

FPGA ； 硬體加速

並列摘要

Before the hardware of a system is available, developers often use a virtual platform to develop software for the system. However, to deliver a fast and accurate simulation of systems is still an important issue that is open for research. And FPGA chips has many benefits such as high power-performance ratio, good at intensive integer operation and can be reconfigured to adapt to different workloads. Such structure has the performance of hardware and the flexibility of software. In the thesis, with FPGA, we accelerate the cache simulation part of VPMU and let user profile a program much faster.

並列關鍵字

FPGA ； Hardware acceleration

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